forked from M-Labs/artiq
drtio: add timeout on FIFO get space request
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@ -1,5 +1,6 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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@ -21,6 +22,7 @@ class _CSRs(AutoCSR):
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self.o_dbg_last_timestamp = CSRStatus(64)
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self.o_reset_channel_status = CSR()
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self.o_wait = CSRStatus()
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self.o_fifo_space_timeout = CSR()
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class RTController(Module):
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@ -96,6 +98,14 @@ class RTController(Module):
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If(sequence_error_set, status_sequence_error.eq(1)),
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]
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signal_fifo_space_timeout = Signal()
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self.sync += [
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If(self.csrs.o_fifo_space_timeout.re, self.csrs.o_fifo_space_timeout.w.eq(0)),
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If(signal_fifo_space_timeout, self.csrs.o_fifo_space_timeout.w.eq(1))
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]
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timeout_counter = WaitTimer(8191)
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self.submodules += timeout_counter
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# TODO: collision, replace, busy
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:]
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@ -154,6 +164,11 @@ class RTController(Module):
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).Else(
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NextState("GET_FIFO_SPACE")
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)
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),
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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signal_fifo_space_timeout.eq(1),
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NextState("IDLE")
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)
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)
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@ -180,8 +195,8 @@ class RTManager(Module, AutoCSR):
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def __init__(self, rt_packets):
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self.request_echo = CSR()
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self.err_present = CSR()
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self.err_code = CSRStatus(8)
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self.packet_err_present = CSR()
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self.packet_err_code = CSRStatus(8)
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self.update_packet_cnt = CSR()
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self.packet_cnt_tx = CSRStatus(32)
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@ -196,9 +211,9 @@ class RTManager(Module, AutoCSR):
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]
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self.comb += [
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self.err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.err_present.re),
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self.err_code.status.eq(rt_packets.error_code)
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self.packet_err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.packet_err_present.re),
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self.packet_err_code.status.eq(rt_packets.error_code)
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]
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self.sync += \
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