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gateware: remove unused configs in targets (not needed with new moninj)

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This commit is contained in:
Sebastien Bourdeauducq 2017-02-25 12:14:56 +08:00
parent 5a16660aa2
commit f017d1771f
4 changed files with 1 additions and 17 deletions
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12
artiq/gateware/targets/kc705_dds.py
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@ -202,7 +202,6 @@ class NIST_CLOCK(_NIST_Ions):
phy = ttl_simple.Output(ams101_dac.ldac) phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("la32_p")) phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy self.submodules += phy
@ -210,7 +209,6 @@ class NIST_CLOCK(_NIST_Ions):
phy = spi.SPIMaster(ams101_dac) phy = spi.SPIMaster(ams101_dac)
self.submodules += phy self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4)) phy, ofifo_depth=4, ififo_depth=4))
@ -220,9 +218,6 @@ class NIST_CLOCK(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128)) phy, ofifo_depth=128, ififo_depth=128))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 11
phy = dds.AD9914(platform.request("dds"), 11, onehot=True) phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
@ -278,14 +273,12 @@ class NIST_QC2(_NIST_Ions):
phy = ttl_simple.Output(ams101_dac.ldac) phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
# add clock generators after RTIO_REGULAR_TTL_COUNT # add clock generators after TTLs
rtio_channels += clock_generators rtio_channels += clock_generators
phy = spi.SPIMaster(ams101_dac) phy = spi.SPIMaster(ams101_dac)
self.submodules += phy self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4)) phy, ofifo_depth=4, ififo_depth=4))
@ -295,9 +288,6 @@ class NIST_QC2(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128)) phy, ofifo_depth=128, ififo_depth=128))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 2
self.config["DDS_CHANNELS_PER_BUS"] = 12
for backplane_offset in range(2): for backplane_offset in range(2):
phy = dds.AD9914( phy = dds.AD9914(
platform.request("dds", backplane_offset), 12, onehot=True) platform.request("dds", backplane_offset), 12, onehot=True)

1
artiq/gateware/targets/kc705_drtio_master.py
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@ -100,7 +100,6 @@ class Master(MiniSoC, AMPSoC):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")

2
artiq/gateware/targets/phaser.py
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@ -218,8 +218,6 @@ class Phaser(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2)) ofifo_depth=2))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy) rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154.sawgs for sawg in self.ad9154.sawgs

3
artiq/gateware/targets/pipistrello.py
View File

@ -198,15 +198,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 15)) phy = ttl_simple.ClockGen(platform.request("ttl", 15))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0)) phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0))
self.submodules += phy self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=64, ififo_depth=64)) phy, ofifo_depth=64, ififo_depth=64))