srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

drtio/gth_ultrascale: fix rtiox clock domain

This commit is contained in:
Sebastien Bourdeauducq 2019-01-03 20:49:38 +08:00
parent 10ebf63c47
commit f007895fad
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/transceiver/gth_ultrascale.py
View File

@ -672,7 +672,7 @@ class GTH(Module, TransceiverInterface):
self.submodules.tx_phase_alignment = GTHTXPhaseAlignement(self.gths) self.submodules.tx_phase_alignment = GTHTXPhaseAlignement(self.gths)
TransceiverInterface.__init__(self, channel_interfaces) TransceiverInterface.__init__(self, channel_interfaces)
self.cd_rtiox = ClockDomain(reset_less=True) self.clock_domains.cd_rtiox = ClockDomain(reset_less=True)
if create_buf: if create_buf:
# GTH PLLs recover on their own from an interrupted clock input, # GTH PLLs recover on their own from an interrupted clock input,
# but be paranoid about HMC7043 noise. # but be paranoid about HMC7043 noise.