From edfae3c4bac7bbbd4d5899ab2f92de9def23fe27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 15 Jun 2018 14:24:31 +0000 Subject: [PATCH] hmc7043: make fpga fabric clocks lvds 2 V common and 1.9 Vpp swing is brutal to the banks (HP 1.8V AMC and RT 1.8V RTM) --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 36 ++++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index e0ab1adc3..dfbf4dfe7 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -163,22 +163,22 @@ pub mod hmc7043 { const SYSREF_DIV: u32 = 128; // 9.375MHz const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz) - // enabled, divider, analog phase shift, digital phase shift - const OUTPUT_CONFIG: [(bool, u32, u8, u8); 14] = [ - (true, DAC_CLK_DIV, 0x0, 0x0), // 0: DAC2_CLK - (true, SYSREF_DIV, 0x0, 0x0), // 1: DAC2_SYSREF - (true, DAC_CLK_DIV, 0x0, 0x0), // 2: DAC1_CLK - (true, SYSREF_DIV, 0x0, 0x0), // 3: DAC1_SYSREF - (false, 0, 0x0, 0x0), // 4: ADC2_CLK - (false, 0, 0x0, 0x0), // 5: ADC2_SYSREF - (false, 0, 0x0, 0x0), // 6: GTP_CLK2 - (true, SYSREF_DIV, 0x0, 0x0), // 7: FPGA_DAC_SYSREF - (true, FPGA_CLK_DIV, 0x0, 0x0), // 8: GTP_CLK1 - (false, 0, 0x0, 0x0), // 9: AMC_MASTER_AUX_CLK - (false, 0, 0x0, 0x0), // 10: RTM_MASTER_AUX_CLK - (false, 0, 0x0, 0x0), // 11: FPGA_ADC_SYSREF - (false, 0, 0x0, 0x0), // 12: ADC1_CLK - (false, 0, 0x0, 0x0), // 13: ADC1_SYSREF + // enabled, divider, analog phase shift, digital phase shift, output config + const OUTPUT_CONFIG: [(bool, u32, u8, u8, u8); 14] = [ + (true, DAC_CLK_DIV, 0x0, 0x0, 0x08), // 0: DAC2_CLK + (true, SYSREF_DIV, 0x0, 0x0, 0x08), // 1: DAC2_SYSREF + (true, DAC_CLK_DIV, 0x0, 0x0, 0x08), // 2: DAC1_CLK + (true, SYSREF_DIV, 0x0, 0x0, 0x08), // 3: DAC1_SYSREF + (false, 0, 0x0, 0x0, 0x08), // 4: ADC2_CLK + (false, 0, 0x0, 0x0, 0x08), // 5: ADC2_SYSREF + (false, 0, 0x0, 0x0, 0x08), // 6: GTP_CLK2 + (true, SYSREF_DIV, 0x0, 0x0, 0x10), // 7: FPGA_DAC_SYSREF, LVDS + (true, FPGA_CLK_DIV, 0x0, 0x0, 0x08), // 8: GTP_CLK1 + (false, 0, 0x0, 0x0, 0x10), // 9: AMC_MASTER_AUX_CLK + (false, 0, 0x0, 0x0, 0x10), // 10: RTM_MASTER_AUX_CLK + (false, 0, 0x0, 0x0, 0x10), // 11: FPGA_ADC_SYSREF, LVDS + (false, 0, 0x0, 0x0, 0x08), // 12: ADC1_CLK + (false, 0, 0x0, 0x0, 0x08), // 13: ADC1_SYSREF ]; @@ -275,7 +275,7 @@ pub mod hmc7043 { for channel in 0..14 { let channel_base = 0xc8 + 0x0a*(channel as u16); - let (enabled, divider, aphase, dphase) = OUTPUT_CONFIG[channel]; + let (enabled, divider, aphase, dphase, outcfg) = OUTPUT_CONFIG[channel]; if enabled { // Only clock channels need to be high-performance @@ -295,7 +295,7 @@ pub mod hmc7043 { } else { write(channel_base + 0x7, 0x01); } - write(channel_base + 0x8, 0x08) + write(channel_base + 0x8, outcfg) } write(0x1, 0x4a); // Reset dividers and FSMs