forked from M-Labs/artiq
sayma: round FTW like Urukul in JDCGSyncDDS
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@ -250,21 +250,20 @@ class JDCGSyncDDS(Module, AutoCSR):
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self.sawgs = []
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ftw = round(2**len(self.coarse_ts)*9e6/150e6)
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ftw = round(2**len(self.coarse_ts)*9e6/600e6)
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parallelism = 4
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mul_1 = Signal.like(self.coarse_ts)
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mul_2 = Signal.like(self.coarse_ts)
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mul_3 = Signal.like(self.coarse_ts)
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self.sync.rtio += [
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mul_1.eq(self.coarse_ts*ftw),
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mul_1.eq(self.coarse_ts*ftw*parallelism),
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mul_2.eq(mul_1),
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mul_3.eq(mul_2)
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]
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phases = [Signal.like(self.coarse_ts) for i in range(parallelism)]
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self.sync.rtio += [phases[i].eq(mul_3 + i*ftw//parallelism)
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for i in range(parallelism)]
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self.sync.rtio += [phases[i].eq(mul_3 + i*ftw) for i in range(parallelism)]
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resolution = 10
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steps = 2**resolution
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