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ad9910: add ram operation unittests

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2019-02-21 14:48:16 +00:00
parent b57cad77ad
commit ec6588174b
1 changed files with 124 additions and 1 deletions

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@ -1,6 +1,8 @@
from artiq.experiment import * from artiq.experiment import *
from artiq.test.hardware_testbench import ExperimentCase from artiq.test.hardware_testbench import ExperimentCase
from artiq.coredevice.ad9910 import _AD9910_REG_FTW, _AD9910_REG_PROFILE0 from artiq.coredevice.ad9910 import (
_AD9910_REG_FTW, _AD9910_REG_PROFILE0, RAM_MODE_RAMPUP,
RAM_DEST_FTW)
from artiq.coredevice.urukul import ( from artiq.coredevice.urukul import (
urukul_sta_smp_err, CFG_CLK_SEL0, CFG_CLK_SEL1) urukul_sta_smp_err, CFG_CLK_SEL0, CFG_CLK_SEL1)
@ -165,6 +167,107 @@ class AD9910Exp(EnvExperiment):
delay(100*us) delay(100*us)
self.set_dataset("ftw", ftw) self.set_dataset("ftw", ftw)
@kernel
def ram_write(self):
n = 1 << 10
write = [0]*n
for i in range(n):
write[i] = i | (i << 16)
read = [0]*n
self.core.break_realtime()
self.dev.cpld.init()
self.dev.init()
self.dev.set_cfr1(ram_enable=0)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.set_profile_ram(
start=0, end=0 + n - 1, step=1,
profile=0, mode=RAM_MODE_RAMPUP)
self.dev.cpld.set_profile(0)
self.dev.cpld.io_update.pulse_mu(8)
delay(1*ms)
self.dev.write_ram(write)
delay(1*ms)
self.dev.read_ram(read)
self.set_dataset("w", write)
self.set_dataset("r", read)
@kernel
def ram_read_overlapping(self):
write = [0]*989
for i in range(len(write)):
write[i] = i
read = [0]*100
offset = 367
self.core.break_realtime()
self.dev.cpld.init()
self.dev.init()
self.dev.set_cfr1(ram_enable=0)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.set_profile_ram(
start=0, end=0 + len(write) - 1, step=1,
profile=0, mode=RAM_MODE_RAMPUP)
self.dev.set_profile_ram(
start=offset, end=offset + len(read) - 1, step=1,
profile=1, mode=RAM_MODE_RAMPUP)
self.dev.cpld.set_profile(0)
self.dev.cpld.io_update.pulse_mu(8)
delay(1*ms)
self.dev.write_ram(write)
delay(1*ms)
self.dev.cpld.set_profile(1)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.read_ram(read)
# RAM profile addresses are apparently aligned
# to the last address of the RAM
start = len(write) - offset - len(read)
end = len(write) - offset
self.set_dataset("w", write[start:end])
self.set_dataset("r", read)
@kernel
def ram_exec(self):
ftw0 = [0x12345678]*10
ftw1 = [0x55aaaa55]*10
self.core.break_realtime()
self.dev.cpld.init()
self.dev.init()
self.dev.set_cfr1(ram_enable=0)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.set_profile_ram(
start=100, end=100 + len(ftw0) - 1, step=1,
profile=3, mode=RAM_MODE_RAMPUP)
self.dev.set_profile_ram(
start=200, end=200 + len(ftw1) - 1, step=1,
profile=4, mode=RAM_MODE_RAMPUP)
self.dev.cpld.set_profile(3)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.write_ram(ftw0)
self.dev.cpld.set_profile(4)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.write_ram(ftw1)
self.dev.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_FTW)
self.dev.cpld.io_update.pulse_mu(8)
self.dev.cpld.set_profile(3)
self.dev.cpld.io_update.pulse_mu(8)
ftw0r = self.dev.read32(_AD9910_REG_FTW)
delay(100*us)
self.dev.cpld.set_profile(4)
self.dev.cpld.io_update.pulse_mu(8)
ftw1r = self.dev.read32(_AD9910_REG_FTW)
self.set_dataset("ftw", [ftw0[0], ftw0r, ftw1[0], ftw1r])
class AD9910Test(ExperimentCase): class AD9910Test(ExperimentCase):
def test_instantiate(self): def test_instantiate(self):
@ -230,3 +333,23 @@ class AD9910Test(ExperimentCase):
def test_profile_readback(self): def test_profile_readback(self):
self.execute(AD9910Exp, "profile_readback") self.execute(AD9910Exp, "profile_readback")
self.assertEqual(self.dataset_mgr.get("ftw"), list(range(8))) self.assertEqual(self.dataset_mgr.get("ftw"), list(range(8)))
def test_ram_write(self):
self.execute(AD9910Exp, "ram_write")
read = self.dataset_mgr.get("r")
write = self.dataset_mgr.get("w")
self.assertEqual(len(read), len(write))
self.assertEqual(read, write)
def test_ram_read_overlapping(self):
self.execute(AD9910Exp, "ram_read_overlapping")
read = self.dataset_mgr.get("r")
write = self.dataset_mgr.get("w")
self.assertEqual(len(read), 100)
self.assertEqual(read, write)
def test_ram_exec(self):
self.execute(AD9910Exp, "ram_exec")
ftw = self.dataset_mgr.get("ftw")
self.assertEqual(ftw[0], ftw[1])
self.assertEqual(ftw[2], ftw[3])