forked from M-Labs/artiq
ad9910: add ram operation unittests
Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -1,6 +1,8 @@
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from artiq.experiment import *
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.coredevice.ad9910 import _AD9910_REG_FTW, _AD9910_REG_PROFILE0
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from artiq.coredevice.ad9910 import (
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_AD9910_REG_FTW, _AD9910_REG_PROFILE0, RAM_MODE_RAMPUP,
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RAM_DEST_FTW)
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from artiq.coredevice.urukul import (
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urukul_sta_smp_err, CFG_CLK_SEL0, CFG_CLK_SEL1)
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@ -165,6 +167,107 @@ class AD9910Exp(EnvExperiment):
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delay(100*us)
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self.set_dataset("ftw", ftw)
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@kernel
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def ram_write(self):
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n = 1 << 10
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write = [0]*n
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for i in range(n):
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write[i] = i | (i << 16)
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read = [0]*n
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=0, end=0 + n - 1, step=1,
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profile=0, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(0)
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self.dev.cpld.io_update.pulse_mu(8)
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delay(1*ms)
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self.dev.write_ram(write)
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delay(1*ms)
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self.dev.read_ram(read)
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self.set_dataset("w", write)
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self.set_dataset("r", read)
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@kernel
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def ram_read_overlapping(self):
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write = [0]*989
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for i in range(len(write)):
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write[i] = i
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read = [0]*100
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offset = 367
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=0, end=0 + len(write) - 1, step=1,
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profile=0, mode=RAM_MODE_RAMPUP)
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self.dev.set_profile_ram(
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start=offset, end=offset + len(read) - 1, step=1,
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profile=1, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(0)
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self.dev.cpld.io_update.pulse_mu(8)
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delay(1*ms)
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self.dev.write_ram(write)
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delay(1*ms)
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self.dev.cpld.set_profile(1)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.read_ram(read)
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# RAM profile addresses are apparently aligned
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# to the last address of the RAM
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start = len(write) - offset - len(read)
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end = len(write) - offset
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self.set_dataset("w", write[start:end])
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self.set_dataset("r", read)
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@kernel
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def ram_exec(self):
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ftw0 = [0x12345678]*10
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ftw1 = [0x55aaaa55]*10
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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self.dev.set_cfr1(ram_enable=0)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.set_profile_ram(
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start=100, end=100 + len(ftw0) - 1, step=1,
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profile=3, mode=RAM_MODE_RAMPUP)
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self.dev.set_profile_ram(
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start=200, end=200 + len(ftw1) - 1, step=1,
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profile=4, mode=RAM_MODE_RAMPUP)
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self.dev.cpld.set_profile(3)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.write_ram(ftw0)
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self.dev.cpld.set_profile(4)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.write_ram(ftw1)
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self.dev.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_FTW)
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self.dev.cpld.io_update.pulse_mu(8)
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self.dev.cpld.set_profile(3)
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self.dev.cpld.io_update.pulse_mu(8)
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ftw0r = self.dev.read32(_AD9910_REG_FTW)
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delay(100*us)
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self.dev.cpld.set_profile(4)
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self.dev.cpld.io_update.pulse_mu(8)
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ftw1r = self.dev.read32(_AD9910_REG_FTW)
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self.set_dataset("ftw", [ftw0[0], ftw0r, ftw1[0], ftw1r])
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class AD9910Test(ExperimentCase):
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def test_instantiate(self):
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@ -230,3 +333,23 @@ class AD9910Test(ExperimentCase):
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def test_profile_readback(self):
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self.execute(AD9910Exp, "profile_readback")
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self.assertEqual(self.dataset_mgr.get("ftw"), list(range(8)))
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def test_ram_write(self):
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self.execute(AD9910Exp, "ram_write")
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read = self.dataset_mgr.get("r")
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write = self.dataset_mgr.get("w")
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self.assertEqual(len(read), len(write))
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self.assertEqual(read, write)
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def test_ram_read_overlapping(self):
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self.execute(AD9910Exp, "ram_read_overlapping")
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read = self.dataset_mgr.get("r")
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write = self.dataset_mgr.get("w")
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self.assertEqual(len(read), 100)
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self.assertEqual(read, write)
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def test_ram_exec(self):
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self.execute(AD9910Exp, "ram_exec")
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ftw = self.dataset_mgr.get("ftw")
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self.assertEqual(ftw[0], ftw[1])
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self.assertEqual(ftw[2], ftw[3])
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