srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

drtio: minor cleanup

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2018-08-30 15:15:32 +08:00
parent 4d73fb5bc9
commit ec62eb9373
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
artiq/gateware/drtio/core.py
View File

@ -128,7 +128,7 @@ class DRTIOSatellite(Module):
class DRTIOMaster(Module):
def __init__(self, chanif, channel_count=1024, fine_ts_width=3):
def __init__(self, chanif, fine_ts_width=3):
self.submodules.link_layer = link_layer.LinkLayer(
chanif.encoder, chanif.decoders)
self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
@ -136,9 +136,8 @@ class DRTIOMaster(Module):
self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
self.submodules.rt_controller = rt_controller_master.RTController(
self.rt_packet, channel_count, fine_ts_width)
self.rt_packet, fine_ts_width)
self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
self.cri = self.rt_controller.cri
self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)
@ -149,3 +148,7 @@ class DRTIOMaster(Module):
self.rt_controller.get_csrs() +
self.rt_manager.get_csrs() +
self.aux_controller.get_csrs())
@property
def cri(self):
return self.rt_controller.cri

2
artiq/gateware/drtio/rt_controller_master.py
View File

@ -45,7 +45,7 @@ class RTIOCounter(Module):
class RTController(Module):
def __init__(self, rt_packet, channel_count, fine_ts_width):
def __init__(self, rt_packet, fine_ts_width):
self.csrs = _CSRs()
self.cri = cri.Interface()