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rtio: test DMA RTIO wait state

This commit is contained in:
Sebastien Bourdeauducq 2016-12-05 18:01:29 +08:00
parent b677c69faf
commit eb8d630148
1 changed files with 7 additions and 0 deletions
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7
artiq/test/gateware/rtio/test_dma.py
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@ -1,4 +1,5 @@
import unittest import unittest
import random
from migen import * from migen import *
from misoc.interconnect import wishbone from misoc.interconnect import wishbone
@ -57,6 +58,7 @@ class TB(Module):
class TestDMA(unittest.TestCase): class TestDMA(unittest.TestCase):
def test_dma_noerror(self): def test_dma_noerror(self):
prng = random.Random(0)
ws = 64 ws = 64
tb = TB(ws) tb = TB(ws)
@ -81,6 +83,11 @@ class TestDMA(unittest.TestCase):
address = yield dut_cri.o_address address = yield dut_cri.o_address
data = yield dut_cri.o_data data = yield dut_cri.o_data
received.append((channel, timestamp, address, data)) received.append((channel, timestamp, address, data))
yield dut_cri.o_status.eq(1)
for i in range(prng.randrange(10)):
yield
yield dut_cri.o_status.eq(0)
else: else:
self.fail("unexpected RTIO command") self.fail("unexpected RTIO command")
yield yield