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sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)

This commit is contained in:
Florent Kermarrec 2018-03-12 11:25:29 +01:00
parent 6dfebd54dd
commit eb6e59b44c
1 changed files with 0 additions and 4 deletions
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4
artiq/gateware/targets/sayma_rtm.py
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@ -159,11 +159,7 @@ class SaymaRTM(Module):
csr_devices.append("serwb_phy_rtm") csr_devices.append("serwb_phy_rtm")
serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes.clk, serwb_phy_rtm.serdes.cd_serwb_serdes.clk,