From eac447278fd788ec2b0462c97292c4fd0580c5d4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 17 Apr 2018 18:48:22 +0800 Subject: [PATCH] kasli: add MITLL variant --- artiq/examples/kasli_mitll/device_db.py | 155 ++++++++++++++++++ artiq/examples/kasli_mitll/repository/demo.py | 52 ++++++ artiq/frontend/artiq_flash.py | 2 +- artiq/gateware/targets/kasli.py | 69 +++++++- 4 files changed, 276 insertions(+), 2 deletions(-) create mode 100644 artiq/examples/kasli_mitll/device_db.py create mode 100644 artiq/examples/kasli_mitll/repository/demo.py diff --git a/artiq/examples/kasli_mitll/device_db.py b/artiq/examples/kasli_mitll/device_db.py new file mode 100644 index 000000000..f828fe8f1 --- /dev/null +++ b/artiq/examples/kasli_mitll/device_db.py @@ -0,0 +1,155 @@ +core_addr = "kasli-2.lab.m-labs.hk" + +device_db = { + "core": { + "type": "local", + "module": "artiq.coredevice.core", + "class": "Core", + "arguments": {"host": core_addr, "ref_period": 1e-9} + }, + "core_log": { + "type": "controller", + "host": "::1", + "port": 1068, + "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr + }, + "core_cache": { + "type": "local", + "module": "artiq.coredevice.cache", + "class": "CoreCache" + }, + "core_dma": { + "type": "local", + "module": "artiq.coredevice.dma", + "class": "CoreDMA" + }, + + "i2c_switch0": { + "type": "local", + "module": "artiq.coredevice.i2c", + "class": "PCA9548", + "arguments": {"address": 0xe0} + }, + "i2c_switch1": { + "type": "local", + "module": "artiq.coredevice.i2c", + "class": "PCA9548", + "arguments": {"address": 0xe2} + }, +} + +for i in range(8): + device_db["ttl" + str(i)] = { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLInOut", + "arguments": {"channel": i}, + } + +device_db.update( + spi_urukul0={ + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 9} + }, + ttl_urukul0_io_update={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 10} + }, + ttl_urukul0_sw0={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 11} + }, + ttl_urukul0_sw1={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 12} + }, + ttl_urukul0_sw2={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 13} + }, + ttl_urukul0_sw3={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 14} + }, + urukul0_cpld={ + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul0", + "io_update_device": "ttl_urukul0_io_update", + "refclk": 125e6, + "clk_sel": 0 + } + } +) + +for i in range(4): + device_db["urukul0_ch" + str(i)] = { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 4 + i, + "cpld_device": "urukul0_cpld", + "sw_device": "ttl_urukul0_sw" + str(i) + } + } + +for i in range(2): + device_db["spi_zotino{}".format(i)] = { + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 15+3*i+0} + }, + device_db["ttl_zotino{}_ldac".format(i)] = { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 15+3*i+1} + }, + device_db["ttl_zotino{}_clr".format(i)] = { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 15+3*i+2} + }, + device_db["zotino{}".format(i)] = { + "type": "local", + "module": "artiq.coredevice.zotino", + "class": "Zotino", + "arguments": { + "spi_device": "spi_zotino{}".format(i), + "ldac_device": "ttl_zotino{}_ldac".format(i), + "clr_device": "ttl_zotino{}_clr".format(i) + } + } + +device_db.update( + led0={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 18} + }, + led1={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 19} + } +) diff --git a/artiq/examples/kasli_mitll/repository/demo.py b/artiq/examples/kasli_mitll/repository/demo.py new file mode 100644 index 000000000..bdb3b9361 --- /dev/null +++ b/artiq/examples/kasli_mitll/repository/demo.py @@ -0,0 +1,52 @@ +from artiq.experiment import * + + +class UrukulTest(EnvExperiment): + def build(self): + self.setattr_device("core") + self.setattr_device("urukul0_cpld") + self.setattr_device("urukul0_ch0") + self.setattr_device("urukul0_ch1") + self.setattr_device("urukul0_ch2") + self.setattr_device("urukul0_ch3") + self.setattr_device("led0") + self.ttl = self.get_device("ttl16") + + @kernel + def run(self): + self.core.reset() + self.ttl.output() + delay(1*us) + + self.urukul0_cpld.init() + self.urukul0_ch0.init() + self.urukul0_ch1.init() + self.urukul0_ch2.init() + self.urukul0_ch3.init() + + delay(1000*us) + self.urukul0_ch0.set(10*MHz) + self.urukul0_ch0.sw.on() + self.urukul0_ch0.set_att(10.) + + delay(1000*us) + self.urukul0_ch1.set(20*MHz, 0.5) + self.urukul0_ch1.sw.on() + self.urukul0_ch1.set_att(8.) + + delay(1000*us) + self.urukul0_ch2.set(30*MHz) + self.urukul0_ch2.sw.on() + self.urukul0_ch2.set_att(6.) + + delay(1000*us) + self.urukul0_ch3.set(40*MHz) + self.urukul0_ch3.sw.on() + self.urukul0_ch3.set_att(4.) + + while True: + with parallel: + self.ttl.pulse(100*ms) + self.urukul0_ch0.sw.pulse(100*ms) + delay(100*ms) + self.led0.pulse(100*ms) diff --git a/artiq/frontend/artiq_flash.py b/artiq/frontend/artiq_flash.py index 4b614aa98..8023dac56 100755 --- a/artiq/frontend/artiq_flash.py +++ b/artiq/frontend/artiq_flash.py @@ -265,7 +265,7 @@ def main(): }, "kasli": { "programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"), - "variants": ["opticlock", "suservo", "sysu", "master", "satellite"], + "variants": ["opticlock", "suservo", "sysu", "mitll", "master", "satellite"], "gateware": ("spi0", 0x000000), "bootloader": ("spi0", 0x400000), "storage": ("spi0", 0x440000), diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index b90680470..a6cd054c3 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -586,6 +586,71 @@ class SYSU(_StandaloneBase): self.add_rtio(rtio_channels) +class MITLL(_StandaloneBase): + def __init__(self, hw_rev=None, **kwargs): + if hw_rev is None: + hw_rev = "v1.1" + _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) + + self.config["SI5324_AS_SYNTHESIZER"] = None + self.config["RTIO_FREQUENCY"] = "125.0" + + platform = self.platform + # TODO: grabber on eem0->eemB eem1->eemA + platform.add_extension(_urukul("eem3", "eem2")) + platform.add_extension(_dio("eem4")) + platform.add_extension(_zotino("eem5")) + platform.add_extension(_zotino("eem6")) + + # EEM4: TTL + rtio_channels = [] + for i in range(8): + pads = platform.request("eem4", i) + phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + # EEM2, EEM3: Urukul + phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"), + self.platform.request("eem3_spi_n")) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + + pads = platform.request("eem3_dds_reset") + self.specials += DifferentialOutput(0, pads.p, pads.n) + + for signal in "io_update sw0 sw1 sw2 sw3".split(): + pads = platform.request("eem3_{}".format(signal)) + phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + # EEM5, EEM6: Zotino + for i in (5, 6): + phy = spi2.SPIMaster(self.platform.request("eem{}_spi_p".format(i)), + self.platform.request("eem{}_spi_n".format(i))) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + + for signal in "ldac_n clr_n".split(): + pads = platform.request("eem{}_{}".format(i, signal)) + phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + for i in (1, 2): + sfp_ctl = platform.request("sfp_ctl", i) + phy = ttl_simple.Output(sfp_ctl.led) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + self.config["HAS_RTIO_LOG"] = None + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + + self.add_rtio(rtio_channels) + + class _RTIOClockMultiplier(Module): def __init__(self, rtio_clk_freq): self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) @@ -895,7 +960,7 @@ def main(): soc_kasli_args(parser) parser.set_defaults(output_dir="artiq_kasli") parser.add_argument("-V", "--variant", default="opticlock", - help="variant: opticlock/suservo/sysu/master/satellite " + help="variant: opticlock/suservo/sysu/mitll/master/satellite " "(default: %(default)s)") args = parser.parse_args() @@ -906,6 +971,8 @@ def main(): cls = SUServo elif variant == "sysu": cls = SYSU + elif variant == "mitll": + cls = MITLL elif variant == "master": cls = Master elif variant == "satellite":