From ea95d914284816532282f84adc07c51578fad8d9 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 9 Nov 2020 17:57:13 +0800
Subject: [PATCH] wrpll: separate collector reset

---
 artiq/firmware/libboard_artiq/wrpll.rs |  5 +++++
 artiq/gateware/drtio/wrpll/core.py     | 12 +++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/artiq/firmware/libboard_artiq/wrpll.rs b/artiq/firmware/libboard_artiq/wrpll.rs
index e31b46ca2..4b0fa9754 100644
--- a/artiq/firmware/libboard_artiq/wrpll.rs
+++ b/artiq/firmware/libboard_artiq/wrpll.rs
@@ -485,6 +485,10 @@ fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> {
             csr::wrpll::main_dcxo_gpio_enable_write(0);
             csr::wrpll::helper_dcxo_errors_write(0xff);
             csr::wrpll::main_dcxo_errors_write(0xff);
+            csr::wrpll::collector_reset_write(0);
+        }
+        clock::spin_us(1_000); // wait for the collector to produce meaningful output
+        unsafe {
             csr::wrpll::filter_reset_write(0);
         }
 
@@ -499,6 +503,7 @@ fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> {
 
         unsafe {
             csr::wrpll::filter_reset_write(1);
+            csr::wrpll::collector_reset_write(1);
         }
         clock::spin_us(50_000);
         unsafe {
diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py
index 0d222768b..52bc91ab7 100644
--- a/artiq/gateware/drtio/wrpll/core.py
+++ b/artiq/gateware/drtio/wrpll/core.py
@@ -51,6 +51,7 @@ class FrequencyCounter(Module, AutoCSR):
 class WRPLL(Module, AutoCSR):
     def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15):
         self.helper_reset = CSRStorage(reset=1)
+        self.collector_reset = CSRStorage(reset=1)
         self.filter_reset = CSRStorage(reset=1)
         self.adpll_offset_helper = CSRStorage(24)
         self.adpll_offset_main = CSRStorage(24)
@@ -69,15 +70,20 @@ class WRPLL(Module, AutoCSR):
         ]
 
         self.clock_domains.cd_helper = ClockDomain()
+        self.clock_domains.cd_collector = ClockDomain()
         self.clock_domains.cd_filter = ClockDomain()
         self.helper_reset.storage.attr.add("no_retiming")
         self.filter_reset.storage.attr.add("no_retiming")
         self.specials += Instance("IBUFGDS",
                 i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
                 o_O=self.cd_helper.clk)
-        self.comb += self.cd_filter.clk.eq(self.cd_helper.clk)
+        self.comb += [
+            self.cd_collector.clk.eq(self.cd_collector.clk),
+            self.cd_filter.clk.eq(self.cd_helper.clk),
+        ]
         self.specials += [
             AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage),
+            AsyncResetSynchronizer(self.cd_collector, self.collector_reset.storage),
             AsyncResetSynchronizer(self.cd_filter, self.filter_reset.storage)
         ]
 
@@ -92,9 +98,9 @@ class WRPLL(Module, AutoCSR):
         self.submodules.ddmtd_ref = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
         self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
 
+        collector_cd = ClockDomainsRenamer("collector")
         filter_cd = ClockDomainsRenamer("filter")
-        helper_cd = ClockDomainsRenamer("helper")
-        self.submodules.collector = helper_cd(Collector(N))
+        self.submodules.collector = collector_cd(Collector(N))
         self.submodules.filter_helper = filter_cd(
             thls.make(filters.helper, data_width=48))
         self.submodules.filter_main = filter_cd(