forked from M-Labs/artiq
pipistrello: tie unused dds.p low
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@ -166,7 +166,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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self.add_constant("DDS_AD9858")
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phy = dds.AD9858(platform.request("dds"), 8)
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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