forked from M-Labs/artiq
Remove one RTIO out channel to free up some space for travis builds to succeed
This commit is contained in:
parent
3108ffeef6
commit
e9092edb98
|
@ -111,7 +111,7 @@ class ARTIQMiniSoC(BaseSoC):
|
||||||
platform.request("ttl_h_tx_en").eq(1)
|
platform.request("ttl_h_tx_en").eq(1)
|
||||||
]
|
]
|
||||||
rtio_ins = [platform.request("pmt") for i in range(2)]
|
rtio_ins = [platform.request("pmt") for i in range(2)]
|
||||||
rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
|
rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
|
||||||
|
|
||||||
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
|
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
|
||||||
self.submodules.rtiophy = rtio.phy.SimplePHY(
|
self.submodules.rtiophy = rtio.phy.SimplePHY(
|
||||||
|
|
Loading…
Reference in New Issue