forked from M-Labs/artiq
hmc7043: disable GTP_CLK1 when not in use
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is not instantiated, and driving a clock then leads to overvoltage.
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@ -171,7 +171,10 @@ pub mod hmc7043 {
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(false, 0, 0x08), // 5: ADC2_SYSREF
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(true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2
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(true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
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#[cfg(hmc7043_enable_clk1)]
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(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
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#[cfg(not(hmc7043_enable_clk1))]
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(false, 0, 0x08), // 8: GTP_CLK1
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(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
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(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
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(true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
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@ -269,6 +269,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.config["HMC7043_ENABLE_CLK1"] = None
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drtio_csr_group = []
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drtio_memory_group = []
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@ -571,6 +572,8 @@ class Satellite(BaseSoC, RTMCommon):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.config["HMC7043_ENABLE_CLK1"] = None
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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