forked from M-Labs/artiq
pipistrello: adhere to pmod interface type 2 layout
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@ -196,10 +196,10 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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pmod = self.platform.request("pmod", 0)
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spi_pins = Module()
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spi_pins.clk = pmod.d[0]
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spi_pins.cs_n = pmod.d[0]
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spi_pins.mosi = pmod.d[1]
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spi_pins.miso = pmod.d[2]
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spi_pins.cs_n = pmod.d[3:]
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spi_pins.clk = pmod.d[3]
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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