From e67a289e2b83342933ae1c3912498dce117eb8ed Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 9 Feb 2018 16:52:48 +0800 Subject: [PATCH] examples: add SAWG sines (DAC synchronization test) --- .../sayma_standalone/repository/sines.py | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 artiq/examples/sayma_standalone/repository/sines.py diff --git a/artiq/examples/sayma_standalone/repository/sines.py b/artiq/examples/sayma_standalone/repository/sines.py new file mode 100644 index 000000000..803164b3d --- /dev/null +++ b/artiq/examples/sayma_standalone/repository/sines.py @@ -0,0 +1,22 @@ +from artiq.experiment import * + + +class SAWGTest(EnvExperiment): + def build(self): + self.setattr_device("core") + self.setattr_device("ttl_sma_out") + self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)] + + @kernel + def run(self): + self.core.reset() + + for sawg in self.sawgs: + delay(1*ms) + sawg.amplitude1.set(.4) + # Do not use a sub-multiple of oscilloscope sample rates. + sawg.frequency0.set(49*MHz) + + while True: + delay(0.5*ms) + self.ttl_sma_out.pulse(0.5*ms)