From e5de5ef4736138284a11339427d12ed7160d492f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 22 Feb 2018 15:18:06 +0800 Subject: [PATCH] kasli: use deterministic RX synchronizer Could not reproduce the "fully broken bitstream" bug. --- artiq/gateware/targets/kasli.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index d5affe656..12e6cb20d 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -21,6 +21,7 @@ from artiq.gateware.amp import AMPSoC from artiq.gateware import rtio from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2 from artiq.gateware.drtio.transceiver import gtp_7series +from artiq.gateware.drtio.xilinx_rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite from artiq.build_soc import build_artiq_soc from artiq import __version__ as artiq_version @@ -476,8 +477,10 @@ class Satellite(BaseSoC): ~self.drtio_transceiver.stable_clkin.storage) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) + self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.drtio0 = rx0(DRTIOSatellite( - self.drtio_transceiver.channels[0], rtio_channels)) + self.drtio_transceiver.channels[0], rtio_channels, + self.rx_synchronizer)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus)