forked from M-Labs/artiq
Merge pull request #1962 from quartiq/miqro
Support MIQRO mode for Phaser
This commit is contained in:
commit
e5c621751f
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@ -9,7 +9,8 @@ Unreleased
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Highlights:
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* Implemented Phaser-servo. This requires recent gateware on Phaser.
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* Implemented Phaser-MIQRO support. This requires the Phaser MIQRO gateware
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variant.
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ARTIQ-7
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-------
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@ -9,6 +9,10 @@ from artiq.coredevice.trf372017 import TRF372017
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PHASER_BOARD_ID = 19
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PHASER_GW_BASE = 1
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PHASER_GW_MIQRO = 2
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PHASER_ADDR_BOARD_ID = 0x00
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PHASER_ADDR_HW_REV = 0x01
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PHASER_ADDR_GW_REV = 0x02
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@ -47,6 +51,12 @@ PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x71 servo coefficients + offset data
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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# 0x72 - 0x78 Miqro channel profile/window memories
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PHASER_ADDR_MIQRO_MEM_ADDR = 0x72
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PHASER_ADDR_MIQRO_MEM_DATA = 0x74
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# Miqro profile memory select
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PHASER_MIQRO_SEL_PROFILE = 1 << 14
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_TRF0 = 1 << 1
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@ -78,6 +88,26 @@ class Phaser:
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Phaser contains a 4 channel, 1 GS/s DAC chip with integrated upconversion,
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quadrature modulation compensation and interpolation features.
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The coredevice RTIO PHY and the Phaser gateware come in different modes
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that have different features. Phaser mode and coredevice PHY mode are both
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selected at their respective gateware compile-time and need to match.
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=============== ============== ===================================
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Phaser gateware Coredevice PHY Features per :class:`PhaserChannel`
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=============== ============== ===================================
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Base <= v0.5 Base Base (5 :class:`PhaserOscillator`)
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Base >= v0.6 Base Base + Servo
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Miqro >= v0.6 Miqro :class:`Miqro`
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=============== ============== ===================================
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The coredevice driver (this class and :class:`PhaserChannel`) exposes
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the superset of all functionality regardless of the Coredevice RTIO PHY
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or Phaser gateware modes. This is to evade type unification limitations.
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Features absent in Coredevice PHY/Phaser gateware will not work and
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should not be accessed.
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**Base mode**
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The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
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MS/s and 14 bit per quadrature. Each data stream supports 5 independent
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numerically controlled IQ oscillators (NCOs, DDSs with 32 bit frequency, 16
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@ -108,6 +138,14 @@ class Phaser:
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absolute phase with respect to other RTIO input and output events
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(see `get_next_frame_mu()`).
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**Miqro mode**
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See :class:`Miqro`
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Here the DAC operates in 4x interpolation.
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**Analog flow**
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The four analog DAC outputs are passed through anti-aliasing filters.
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In the baseband variant, the even/in-phase DAC channels feed 31.5 dB range
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@ -125,6 +163,8 @@ class Phaser:
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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**Servo**
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Each phaser output channel features a servo to control the RF output amplitude
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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impulse response) filter fed by the ADC and a multiplier that scales the I
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@ -203,6 +243,7 @@ class Phaser:
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self.clk_sel = clk_sel
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self.tune_fifo_offset = tune_fifo_offset
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self.sync_dly = sync_dly
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self.gw_rev = -1 # discovered in init()
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self.dac_mmap = DAC34H84(dac).get_mmap()
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@ -226,9 +267,9 @@ class Phaser:
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delay(.1*ms) # slack
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is_baseband = hw_rev & PHASER_HW_REV_VARIANT
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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self.gw_rev = self.read8(PHASER_ADDR_GW_REV)
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if debug:
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print("gw_rev:", gw_rev)
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print("gw_rev:", self.gw_rev)
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self.core.break_realtime()
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delay(.1*ms) # slack
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@ -346,36 +387,40 @@ class Phaser:
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if channel.get_att_mu() != 0x5a:
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raise ValueError("attenuator test failed")
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delay(.1*ms)
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channel.set_att_mu(0x00) # minimum attenuation
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channel.set_att_mu(0x00) # maximum attenuation
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channel.set_servo(profile=0, enable=0, hold=1)
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# test oscillators and DUC
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for i in range(len(channel.oscillator)):
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oscillator = channel.oscillator[i]
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asf = 0
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if i == 0:
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asf = 0x7fff
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# 6pi/4 phase
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oscillator.set_amplitude_phase_mu(asf=asf, pow=0xc000, clr=1)
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if self.gw_rev == PHASER_GW_BASE:
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# test oscillators and DUC
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for i in range(len(channel.oscillator)):
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oscillator = channel.oscillator[i]
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asf = 0
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if i == 0:
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asf = 0x7fff
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# 6pi/4 phase
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oscillator.set_amplitude_phase_mu(asf=asf, pow=0xc000, clr=1)
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delay(1*us)
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# 3pi/4
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channel.set_duc_phase_mu(0x6000)
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channel.set_duc_cfg(select=0, clr=1)
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self.duc_stb()
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delay(.1*ms) # settle link, pipeline and impulse response
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data = channel.get_dac_data()
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delay(1*us)
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# 3pi/4
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channel.set_duc_phase_mu(0x6000)
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channel.set_duc_cfg(select=0, clr=1)
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self.duc_stb()
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delay(.1*ms) # settle link, pipeline and impulse response
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data = channel.get_dac_data()
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delay(1*us)
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channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000,
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clr=1)
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delay(.1*ms)
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sqrt2 = 0x5a81 # 0x7fff/sqrt(2)
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data_i = data & 0xffff
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data_q = (data >> 16) & 0xffff
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# allow ripple
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if (data_i < sqrt2 - 30 or data_i > sqrt2 or
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abs(data_i - data_q) > 2):
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000,
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clr=1)
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delay(.1*ms)
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sqrt2 = 0x5a81 # 0x7fff/sqrt(2)
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data_i = data & 0xffff
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data_q = (data >> 16) & 0xffff
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# allow ripple
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if (data_i < sqrt2 - 30 or data_i > sqrt2 or
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abs(data_i - data_q) > 2):
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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if self.gw_rev == PHASER_GW_MIQRO:
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channel.miqro.reset()
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if is_baseband:
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continue
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@ -782,6 +827,8 @@ class Phaser:
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if good & (1 << o):
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sum += o
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count += 1
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if count == 0:
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raise ValueError("no good fifo offset")
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best = ((sum // count) + offset) % 8
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self.dac_write(0x09, (config9 & 0x1fff) | (best << 13))
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return best
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@ -792,8 +839,9 @@ class PhaserChannel:
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A Phaser channel contains:
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* multiple oscillators (in the coredevice phy),
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* multiple :class:`PhaserOscillator` (in the coredevice phy),
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* an interpolation chain and digital upconverter (DUC) on Phaser,
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* a :class:`Miqro` instance on Phaser,
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* several channel-specific settings in the DAC:
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* quadrature modulation compensation QMC
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@ -805,6 +853,7 @@ class PhaserChannel:
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Attributes:
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* :attr:`oscillator`: List of five :class:`PhaserOscillator`.
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* :attr:`miqro`: A :class:`Miqro`.
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.. note:: The amplitude sum of the oscillators must be less than one to
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avoid clipping or overflow. If any of the DDS or DUC frequencies are
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@ -817,6 +866,8 @@ class PhaserChannel:
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changes in oscillator parameters, the overshoot can lead to clipping
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or overflow after the interpolation. Either band-limit any changes
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in the oscillator parameters or back off the amplitude sufficiently.
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Miqro is not affected by this. But both the oscillators and Miqro can
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be affected by intrinsic overshoot of the interpolator on the DAC.
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"""
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kernel_invariants = {"index", "phaser", "trf_mmap"}
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@ -826,6 +877,7 @@ class PhaserChannel:
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self.trf_mmap = TRF372017(trf).get_mmap()
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self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
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self.miqro = Miqro(self)
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@kernel
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def get_dac_data(self) -> TInt32:
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@ -1139,7 +1191,7 @@ class PhaserChannel:
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for data in [b0, b1, a1, offset]:
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self.phaser.write16(addr, data)
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addr += 2
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@kernel
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def set_iir(self, profile, kp, ki=0., g=0., x_offset=0., y_offset=0.):
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"""Set servo profile IIR coefficients.
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@ -1149,8 +1201,8 @@ class PhaserChannel:
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Gains are given in units of output full per scale per input full scale.
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.. note:: Due to inherent constraints of the fixed point datatypes and IIR
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filters, the ``x_offset`` (setpoint) resolution depends on the selected gains.
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Low ``ki`` gains will lead to a low ``x_offset`` resolution.
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filters, the ``x_offset`` (setpoint) resolution depends on the selected
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gains. Low ``ki`` gains will lead to a low ``x_offset`` resolution.
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The transfer function is (up to time discretization and
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coefficient quantization errors):
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@ -1269,3 +1321,305 @@ class PhaserOscillator:
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raise ValueError("amplitude out of bounds")
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pow = int32(round(phase*(1 << 16)))
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self.set_amplitude_phase_mu(asf, pow, clr)
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class Miqro:
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"""
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Miqro pulse generator.
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A Miqro instance represents one RF output. The DSP components are fully
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contained in the Phaser gateware. The output is generated by with
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the following data flow:
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**Oscillators**
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* There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
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* Each oscillator outputs one tone at any given time
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* I/Q (quadrature, a.k.a. complex) 2x16 bit signed data
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at tau = 4 ns sample intervals, 250 MS/s, Nyquist 125 MHz, bandwidth 200 MHz
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(from f = -100..+100 MHz, taking into account the interpolation anti-aliasing
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filters in subsequent interpolators),
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* 32 bit frequency (f) resolution (~ 1/16 Hz),
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* 16 bit unsigned amplitude (a) resolution
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* 16 bit phase offset (p) resolution
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* The output phase p' of each oscillator at time t (boot/reset/initialization of the
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device at t=0) is then p' = f*t + p (mod 1 turn) where f and p are the (currently
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active) profile frequency and phase offset.
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* Note: The terms "phase coherent" and "phase tracking" are defined to refer to this
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choice of oscillator output phase p'. Note that the phase offset p is not relative to
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(on top of previous phase/profiles/oscillator history).
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It is "absolute" in the sense that frequency f and phase offset p fully determine
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oscillator output phase p' at time t. This is unlike typical DDS behavior.
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* Frequency, phase, and amplitude of each oscillator are configurable by selecting one of
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n_profile = 32 profiles 0..n_profile-1. This selection is fast and can be done for
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each pulse. The phase coherence defined above is guaranteed for each
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profile individually.
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* Note: one profile per oscillator (usually profile index 0) should be reserved
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for the NOP (no operation, identity) profile, usually with zero amplitude.
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* Data for each profile for each oscillator can be configured
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individually. Storing profile data should be considered "expensive".
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* Note: The annotation that some operation is "expensive" does not mean it is
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impossible, just that it may take a significant amount of time and
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resources to execute such that it may be impractical when used often or
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during fast pulse sequences. They are intended for use in calibration and
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initialization.
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**Summation**
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* The oscillator outputs are added together (wrapping addition).
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* The user must ensure that the sum of oscillators outputs does not exceed the
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data range. In general that means that the sum of the amplitudes must not
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exceed one.
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**Shaper**
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* The summed complex output stream is then multiplied with a the complex-valued
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output of a triggerable shaper.
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* Triggering the shaper corresponds to passing a pulse from all oscillators to
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the RF output.
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* Selected profiles become active simultaneously (on the same output sample) when
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triggering the shaper with the first shaper output sample.
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* The shaper reads (replays) window samples from a memory of size n_window = 1 << 10.
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* The window memory can be segmented by choosing different start indices
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to support different windows.
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* Each window memory segment starts with a header determining segment
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length and interpolation parameters.
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* The window samples are interpolated by a factor (rate change) between 1 and
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r = 1 << 12.
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* The interpolation order is constant, linear, quadratic, or cubic. This
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corresponds to interpolation modes from rectangular window (1st order CIC)
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or zero order hold) to Parzen window (4th order CIC or cubic spline).
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* This results in support for single shot pulse lengths (envelope support) between
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tau and a bit more than r * n_window * tau = (1 << 12 + 10) tau ~ 17 ms.
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* Windows can be configured to be head-less and/or tail-less, meaning, they
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do not feed zero-amplitude samples into the shaper before and after
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each window respectively. This is used to implement pulses with arbitrary
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length or CW output.
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**Overall properties**
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* The DAC may upconvert the signal by applying a frequency offset f1 with
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phase p1.
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* In the Upconverter Phaser variant, the analog quadrature upconverter
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applies another frequency of f2 and phase p2.
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* The resulting phase of the signal from one oscillator at the SMA output is
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(f + f1 + f2)*t + p + s(t - t0) + p1 + p2 (mod 1 turn)
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where s(t - t0) is the phase of the interpolated
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shaper output, and t0 is the trigger time (fiducial of the shaper).
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Unsurprisingly the frequency is the derivative of the phase.
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* Group delays between pulse parameter updates are matched across oscillators,
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shapers, and channels.
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* The minimum time to change profiles and phase offsets is ~128 ns (estimate, TBC).
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This is the minimum pulse interval.
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The sustained pulse rate of the RTIO PHY/Fastlink is one pulse per Fastlink frame
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(may be increased, TBC).
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"""
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def __init__(self, channel):
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self.channel = channel
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self.base_addr = (self.channel.phaser.channel_base + 1 +
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self.channel.index) << 8
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@kernel
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def reset(self):
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"""Establish no-output profiles and no-output window and execute them.
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This establishes the first profile (index 0) on all oscillators as zero
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amplitude, creates a trivial window (one sample with zero amplitude,
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minimal interpolation), and executes a corresponding pulse.
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"""
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for osc in range(16):
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self.set_profile_mu(osc, profile=0, ftw=0, asf=0)
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delay(20*us)
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self.set_window_mu(start=0, iq=[0], order=0)
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self.pulse(window=0, profiles=[0])
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@kernel
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def set_profile_mu(self, oscillator, profile, ftw, asf, pow_=0):
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"""Store an oscillator profile (machine units).
|
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|
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:param oscillator: Oscillator index (0 to 15)
|
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:param profile: Profile index (0 to 31)
|
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:param ftw: Frequency tuning word (32 bit signed integer on a 250 MHz clock)
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:param asf: Amplitude scale factor (16 bit unsigned integer)
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:param pow_: Phase offset word (16 bit integer)
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"""
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if oscillator >= 16:
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raise ValueError("invalid oscillator index")
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if profile >= 32:
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raise ValueError("invalid profile index")
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self.channel.phaser.write16(PHASER_ADDR_MIQRO_MEM_ADDR,
|
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(self.channel.index << 15) | PHASER_MIQRO_SEL_PROFILE |
|
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(oscillator << 6) | (profile << 1))
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self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA, ftw)
|
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self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA,
|
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(asf & 0xffff) | (pow_ << 16))
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|
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@kernel
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def set_profile(self, oscillator, profile, frequency, amplitude, phase=0.):
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"""Store an oscillator profile.
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|
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:param oscillator: Oscillator index (0 to 15)
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:param profile: Profile index (0 to 31)
|
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:param frequency: Frequency in Hz (passband -100 to 100 MHz).
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Interpreted in the Nyquist sense, i.e. aliased.
|
||||
:param amplitude: Amplitude in units of full scale (0. to 1.)
|
||||
:param phase: Phase in turns. See :class:`Miqro` for a definition of
|
||||
phase in this context.
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||||
:return: The quantized 32 bit frequency tuning word
|
||||
"""
|
||||
ftw = int32(round(frequency*((1 << 30)/(62.5*MHz))))
|
||||
asf = int32(round(amplitude*0xffff))
|
||||
if asf < 0 or asf > 0xffff:
|
||||
raise ValueError("amplitude out of bounds")
|
||||
pow_ = int32(round(phase*(1 << 16)))
|
||||
self.set_profile_mu(oscillator, profile, ftw, asf, pow_)
|
||||
return ftw
|
||||
|
||||
@kernel
|
||||
def set_window_mu(self, start, iq, rate=1, shift=0, order=3, head=1, tail=1):
|
||||
"""Store a window segment (machine units)
|
||||
|
||||
:param start: Window start address (0 to 0x3ff)
|
||||
:param iq: List of IQ window samples. Each window sample is an integer
|
||||
containing the signed I part in the 16 LSB and the signed Q part in
|
||||
the 16 MSB. The maximum window length is 0x3fe. The user must
|
||||
ensure that this window does not overlap with other windows in the
|
||||
memory.
|
||||
:param rate: Interpolation rate change (1 to 1 << 12)
|
||||
:param shift: Interpolator amplitude gain compensation in powers of 2 (0 to 63)
|
||||
:param order: Interpolation order from 0 (corresponding to
|
||||
constant/rectangular window/zero-order-hold/1st order CIC interpolation)
|
||||
to 3 (corresponding to cubic/Parzen window/4th order CIC interpolation)
|
||||
:param head: Update the interpolator settings and clear its state at the start
|
||||
of the window. This also implies starting the envelope from zero.
|
||||
:param tail: Feed zeros into the interpolator after the window samples.
|
||||
In the absence of further pulses this will return the output envelope
|
||||
to zero with the chosen interpolation.
|
||||
:return: Next available window memory address after this segment.
|
||||
"""
|
||||
if start >= 1 << 10:
|
||||
raise ValueError("start out of bounds")
|
||||
if len(iq) >= 1 << 10:
|
||||
raise ValueError("window length out of bounds")
|
||||
if rate < 1 or rate > 1 << 12:
|
||||
raise ValueError("rate out of bounds")
|
||||
if shift > 0x3f:
|
||||
raise ValueError("shift out of bounds")
|
||||
if order > 3:
|
||||
raise ValueError("order out of bounds")
|
||||
self.channel.phaser.write16(PHASER_ADDR_MIQRO_MEM_ADDR,
|
||||
(self.channel.index << 15) | start)
|
||||
self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA,
|
||||
(len(iq) & 0x3ff) |
|
||||
((rate - 1) << 10) |
|
||||
(shift << 22) |
|
||||
(order << 28) |
|
||||
((head & 1) << 30) |
|
||||
((tail & 1) << 31)
|
||||
)
|
||||
for iqi in iq:
|
||||
self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA, iqi)
|
||||
delay(20*us) # slack for long windows
|
||||
return (start + 1 + len(iq)) & 0x3ff
|
||||
|
||||
@kernel
|
||||
def set_window(self, start, iq, period=4*ns, order=3, head=1, tail=1):
|
||||
"""Store a window segment
|
||||
|
||||
:param start: Window start address (0 to 0x3ff)
|
||||
:param iq: List of IQ window samples. Each window sample is a pair of
|
||||
two float numbers -1 to 1, one for each I and Q in units of full scale.
|
||||
The maximum window length is 0x3fe. The user must ensure that this window
|
||||
does not overlap with other windows in the memory.
|
||||
:param period: Desired window sample period in SI units (4*ns to (4 << 12)*ns).
|
||||
:param order: Interpolation order from 0 (corresponding to
|
||||
constant/zero-order-hold/1st order CIC interpolation) to 3 (corresponding
|
||||
to cubic/Parzen/4th order CIC interpolation)
|
||||
:param head: Update the interpolator settings and clear its state at the start
|
||||
of the window. This also implies starting the envelope from zero.
|
||||
:param tail: Feed zeros into the interpolator after the window samples.
|
||||
In the absence of further pulses this will return the output envelope
|
||||
to zero with the chosen interpolation.
|
||||
:return: Actual sample period in SI units
|
||||
"""
|
||||
rate = int32(round(period/(4*ns)))
|
||||
gain = 1.
|
||||
for _ in range(order):
|
||||
gain *= rate
|
||||
shift = 0
|
||||
while gain >= 2.:
|
||||
shift += 1
|
||||
gain *= .5
|
||||
scale = ((1 << 15) - 1)/gain
|
||||
iq_mu = [
|
||||
(int32(round(iqi[0]*scale)) & 0xffff) |
|
||||
(int32(round(iqi[1]*scale)) << 16)
|
||||
for iqi in iq
|
||||
]
|
||||
self.set_window_mu(start, iq_mu, rate, shift, order, head, tail)
|
||||
return (len(iq) + order)*rate*4*ns
|
||||
|
||||
@kernel
|
||||
def encode(self, window, profiles, data):
|
||||
"""Encode window and profile selection
|
||||
|
||||
:param window: Window start address (0 to 0x3ff)
|
||||
:param profiles: List of profile indices for the oscillators. Maximum
|
||||
length 16. Unused oscillators will be set to profile 0.
|
||||
:param data: List of integers to store the encoded data words into.
|
||||
Unused entries will remain untouched. Must contain at least three
|
||||
lements if all oscillators are used and should be initialized to
|
||||
zeros.
|
||||
:return: Number of words from `data` used.
|
||||
"""
|
||||
if len(profiles) > 16:
|
||||
raise ValueError("too many oscillators")
|
||||
if window > 0x3ff:
|
||||
raise ValueError("window start out of bounds")
|
||||
data[0] = window
|
||||
word = 0
|
||||
idx = 10
|
||||
for profile in profiles:
|
||||
if profile > 0x1f:
|
||||
raise ValueError("profile out of bounds")
|
||||
if idx > 32 - 5:
|
||||
word += 1
|
||||
idx = 0
|
||||
data[word] |= profile << idx
|
||||
idx += 5
|
||||
return word + 1
|
||||
|
||||
@kernel
|
||||
def pulse_mu(self, data):
|
||||
"""Emit a pulse (encoded)
|
||||
|
||||
The pulse fiducial timing resolution is 4 ns.
|
||||
|
||||
:param data: List of up to 3 words containing an encoded MIQRO pulse as
|
||||
returned by :meth:`encode`.
|
||||
"""
|
||||
word = len(data)
|
||||
delay_mu(-8*word) # back shift to align
|
||||
while word > 0:
|
||||
word -= 1
|
||||
delay_mu(8)
|
||||
# final write sets pulse stb
|
||||
rtio_output(self.base_addr + word, data[word])
|
||||
|
||||
@kernel
|
||||
def pulse(self, window, profiles):
|
||||
"""Emit a pulse
|
||||
|
||||
This encodes the window and profiles (see :meth:`encode`) and emits them
|
||||
(see :meth:`pulse_mu`).
|
||||
|
||||
:param window: Window start address (0 to 0x3ff)
|
||||
:param profiles: List of profile indices for the oscillators. Maximum
|
||||
length 16. Unused oscillators will select profile 0.
|
||||
"""
|
||||
data = [0, 0, 0]
|
||||
words = self.encode(window, profiles, data)
|
||||
self.pulse_mu(data[:words])
|
||||
|
|
|
@ -559,6 +559,13 @@ class PeripheralManager:
|
|||
return 1
|
||||
|
||||
def process_phaser(self, rtio_offset, peripheral):
|
||||
mode = peripheral.get("mode", "base")
|
||||
if mode == "miqro":
|
||||
dac = ', "dac": {"pll_m": 16, "pll_n": 3, "interpolation": 2}'
|
||||
n_channels = 3
|
||||
else:
|
||||
dac = ""
|
||||
n_channels = 5
|
||||
self.gen("""
|
||||
device_db["{name}"] = {{
|
||||
"type": "local",
|
||||
|
@ -566,12 +573,13 @@ class PeripheralManager:
|
|||
"class": "Phaser",
|
||||
"arguments": {{
|
||||
"channel_base": 0x{channel:06x},
|
||||
"miso_delay": 1,
|
||||
"miso_delay": 1{dac}
|
||||
}}
|
||||
}}""",
|
||||
name=self.get_name("phaser"),
|
||||
dac=dac,
|
||||
channel=rtio_offset)
|
||||
return 5
|
||||
return n_channels
|
||||
|
||||
def process_hvamp(self, rtio_offset, peripheral):
|
||||
hvamp_name = self.get_name("hvamp")
|
||||
|
|
|
@ -8,6 +8,7 @@ import sys
|
|||
|
||||
from artiq.experiment import *
|
||||
from artiq.coredevice.ad9910 import AD9910, SyncDataEeprom
|
||||
from artiq.coredevice.phaser import PHASER_GW_BASE, PHASER_GW_MIQRO
|
||||
from artiq.master.databases import DeviceDB
|
||||
from artiq.master.worker_db import DeviceManager
|
||||
|
||||
|
@ -570,20 +571,37 @@ class SinaraTester(EnvExperiment):
|
|||
self.core.break_realtime()
|
||||
phaser.init()
|
||||
delay(1*ms)
|
||||
phaser.channel[0].set_duc_frequency(duc)
|
||||
phaser.channel[0].set_duc_cfg()
|
||||
phaser.channel[0].set_att(6*dB)
|
||||
phaser.channel[1].set_duc_frequency(-duc)
|
||||
phaser.channel[1].set_duc_cfg()
|
||||
phaser.channel[1].set_att(6*dB)
|
||||
phaser.duc_stb()
|
||||
delay(1*ms)
|
||||
for i in range(len(osc)):
|
||||
phaser.channel[0].oscillator[i].set_frequency(osc[i])
|
||||
phaser.channel[0].oscillator[i].set_amplitude_phase(.2)
|
||||
phaser.channel[1].oscillator[i].set_frequency(-osc[i])
|
||||
phaser.channel[1].oscillator[i].set_amplitude_phase(.2)
|
||||
if phaser.gw_rev == PHASER_GW_BASE:
|
||||
phaser.channel[0].set_duc_frequency(duc)
|
||||
phaser.channel[0].set_duc_cfg()
|
||||
phaser.channel[0].set_att(6*dB)
|
||||
phaser.channel[1].set_duc_frequency(-duc)
|
||||
phaser.channel[1].set_duc_cfg()
|
||||
phaser.channel[1].set_att(6*dB)
|
||||
phaser.duc_stb()
|
||||
delay(1*ms)
|
||||
for i in range(len(osc)):
|
||||
phaser.channel[0].oscillator[i].set_frequency(osc[i])
|
||||
phaser.channel[0].oscillator[i].set_amplitude_phase(.2)
|
||||
phaser.channel[1].oscillator[i].set_frequency(-osc[i])
|
||||
phaser.channel[1].oscillator[i].set_amplitude_phase(.2)
|
||||
delay(1*ms)
|
||||
elif phaser.gw_rev == PHASER_GW_MIQRO:
|
||||
for ch in range(2):
|
||||
phaser.channel[ch].set_att(6*dB)
|
||||
phaser.channel[ch].set_duc_cfg()
|
||||
sign = 1. - 2.*ch
|
||||
for i in range(len(osc)):
|
||||
phaser.channel[ch].miqro.set_profile(i, profile=1,
|
||||
frequency=sign*(duc + osc[i]), amplitude=1./len(osc))
|
||||
delay(100*us)
|
||||
phaser.channel[ch].miqro.set_window(
|
||||
start=0x000, iq=[[1., 0.]], order=0, tail=0)
|
||||
phaser.channel[ch].miqro.pulse(
|
||||
window=0x000, profiles=[1 for _ in range(len(osc))])
|
||||
delay(1*ms)
|
||||
else:
|
||||
raise ValueError
|
||||
|
||||
@kernel
|
||||
def phaser_led_wave(self, phasers):
|
||||
|
|
|
@ -709,20 +709,33 @@ class Phaser(_EEM):
|
|||
) for pol in "pn"]
|
||||
|
||||
@classmethod
|
||||
def add_std(cls, target, eem, iostandard=default_iostandard):
|
||||
def add_std(cls, target, eem, mode="base", iostandard=default_iostandard):
|
||||
cls.add_extension(target, eem, iostandard=iostandard)
|
||||
|
||||
phy = phaser.Phaser(
|
||||
target.platform.request("phaser{}_ser_p".format(eem)),
|
||||
target.platform.request("phaser{}_ser_n".format(eem)))
|
||||
target.submodules += phy
|
||||
target.rtio_channels.extend([
|
||||
rtio.Channel.from_phy(phy, ififo_depth=4),
|
||||
rtio.Channel.from_phy(phy.ch0.frequency),
|
||||
rtio.Channel.from_phy(phy.ch0.phase_amplitude),
|
||||
rtio.Channel.from_phy(phy.ch1.frequency),
|
||||
rtio.Channel.from_phy(phy.ch1.phase_amplitude),
|
||||
])
|
||||
if mode == "base":
|
||||
phy = phaser.Base(
|
||||
target.platform.request("phaser{}_ser_p".format(eem)),
|
||||
target.platform.request("phaser{}_ser_n".format(eem)))
|
||||
target.submodules += phy
|
||||
target.rtio_channels.extend([
|
||||
rtio.Channel.from_phy(phy, ififo_depth=4),
|
||||
rtio.Channel.from_phy(phy.ch0.frequency),
|
||||
rtio.Channel.from_phy(phy.ch0.phase_amplitude),
|
||||
rtio.Channel.from_phy(phy.ch1.frequency),
|
||||
rtio.Channel.from_phy(phy.ch1.phase_amplitude),
|
||||
])
|
||||
elif mode == "miqro":
|
||||
phy = phaser.Miqro(
|
||||
target.platform.request("phaser{}_ser_p".format(eem)),
|
||||
target.platform.request("phaser{}_ser_n".format(eem)))
|
||||
target.submodules += phy
|
||||
target.rtio_channels.extend([
|
||||
rtio.Channel.from_phy(phy, ififo_depth=4),
|
||||
rtio.Channel.from_phy(phy.ch0),
|
||||
rtio.Channel.from_phy(phy.ch1),
|
||||
])
|
||||
else:
|
||||
raise ValueError("invalid mode", mode)
|
||||
|
||||
|
||||
class HVAmp(_EEM):
|
||||
|
|
|
@ -123,13 +123,14 @@ def peripheral_fastino(module, peripheral, **kwargs):
|
|||
def peripheral_phaser(module, peripheral, **kwargs):
|
||||
if len(peripheral["ports"]) != 1:
|
||||
raise ValueError("wrong number of ports")
|
||||
eem.Phaser.add_std(module, peripheral["ports"][0], **kwargs)
|
||||
eem.Phaser.add_std(module, peripheral["ports"][0],
|
||||
peripheral.get("mode", "base"), **kwargs)
|
||||
|
||||
|
||||
def peripheral_hvamp(module, peripheral, **kwargs):
|
||||
if len(peripheral["ports"]) != 1:
|
||||
raise ValueError("wrong number of ports")
|
||||
eem.HVAmp.add_std(module, peripheral["ports"][0],
|
||||
eem.HVAmp.add_std(module, peripheral["ports"][0],
|
||||
ttl_simple.Output, **kwargs)
|
||||
|
||||
|
||||
|
|
|
@ -27,7 +27,7 @@ class DDSChannel(Module):
|
|||
[Cat(i.a, i.clr, i.p) for i in self.dds.i])
|
||||
|
||||
|
||||
class Phaser(Module):
|
||||
class Base(Module):
|
||||
def __init__(self, pins, pins_n):
|
||||
self.rtlink = rtlink.Interface(
|
||||
rtlink.OInterface(data_width=8, address_width=8,
|
||||
|
@ -87,3 +87,93 @@ class Phaser(Module):
|
|||
self.rtlink.i.stb.eq(re_dly[0] & self.serializer.stb),
|
||||
self.rtlink.i.data.eq(self.serializer.readback),
|
||||
]
|
||||
|
||||
|
||||
class MiqroChannel(Module):
|
||||
def __init__(self):
|
||||
self.rtlink = rtlink.Interface(
|
||||
rtlink.OInterface(data_width=30, address_width=2, fine_ts_width=1,
|
||||
enable_replace=False))
|
||||
self.pulse = Signal(128)
|
||||
self.ack = Signal()
|
||||
regs = [Signal(30, reset_less=True) for _ in range(3)]
|
||||
dt = Signal(7, reset_less=True)
|
||||
stb = Signal()
|
||||
pulse = Cat(stb, dt, regs)
|
||||
assert len(self.pulse) >= len(pulse)
|
||||
self.comb += [
|
||||
self.pulse.eq(pulse),
|
||||
self.rtlink.o.busy.eq(stb & ~self.ack),
|
||||
]
|
||||
self.sync.rtio += [
|
||||
If(~stb,
|
||||
dt.eq(dt + 2),
|
||||
),
|
||||
If(self.ack,
|
||||
dt[1:].eq(0),
|
||||
stb.eq(0),
|
||||
If(stb,
|
||||
[r.eq(0) for r in regs],
|
||||
),
|
||||
),
|
||||
If(self.rtlink.o.stb,
|
||||
Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
|
||||
If(self.rtlink.o.address == 0,
|
||||
dt[0].eq(self.rtlink.o.fine_ts),
|
||||
stb.eq(1),
|
||||
),
|
||||
),
|
||||
]
|
||||
|
||||
|
||||
class Miqro(Module):
|
||||
def __init__(self, pins, pins_n):
|
||||
self.rtlink = rtlink.Interface(
|
||||
rtlink.OInterface(data_width=8, address_width=8,
|
||||
enable_replace=False),
|
||||
rtlink.IInterface(data_width=10))
|
||||
|
||||
self.submodules.ch0 = MiqroChannel()
|
||||
self.submodules.ch1 = MiqroChannel()
|
||||
|
||||
self.submodules.serializer = SerDes(
|
||||
n_data=8, t_clk=8, d_clk=0b00001111,
|
||||
n_frame=10, n_crc=6, poly=0x2f)
|
||||
self.submodules.intf = SerInterface(pins, pins_n)
|
||||
self.comb += [
|
||||
Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
|
||||
self.serializer.data[-1].eq(self.intf.data[-1]),
|
||||
]
|
||||
|
||||
header = Record([
|
||||
("we", 1),
|
||||
("addr", 7),
|
||||
("data", 8),
|
||||
("type", 4)
|
||||
])
|
||||
self.comb += [
|
||||
self.serializer.payload.eq(Cat(
|
||||
header.raw_bits(),
|
||||
self.ch0.pulse,
|
||||
self.ch1.pulse,
|
||||
)),
|
||||
self.ch0.ack.eq(self.serializer.stb),
|
||||
self.ch1.ack.eq(self.serializer.stb),
|
||||
]
|
||||
|
||||
re_dly = Signal(3) # stage, send, respond
|
||||
self.sync.rtio += [
|
||||
header.type.eq(3), # body type is miqro pulse data
|
||||
If(self.serializer.stb,
|
||||
header.we.eq(0),
|
||||
re_dly.eq(re_dly[1:]),
|
||||
),
|
||||
If(self.rtlink.o.stb,
|
||||
re_dly[-1].eq(~self.rtlink.o.address[-1]),
|
||||
header.we.eq(self.rtlink.o.address[-1]),
|
||||
header.addr.eq(self.rtlink.o.address),
|
||||
header.data.eq(self.rtlink.o.data),
|
||||
),
|
||||
self.rtlink.i.stb.eq(re_dly[0] & self.serializer.stb),
|
||||
self.rtlink.i.data.eq(self.serializer.readback),
|
||||
]
|
||||
|
|
Loading…
Reference in New Issue