From e54dd088218cef8f6042e29465fc4fb0106b863c Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 10 Feb 2021 15:32:09 +0800
Subject: [PATCH] metlino,sayma: adapt to new EEM API

This also enables 4X SERDES TTLs.
---
 artiq/gateware/targets/metlino.py   | 15 +++++++++------
 artiq/gateware/targets/sayma_amc.py |  9 +++++++--
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py
index 2139278ef..4f609e1c7 100755
--- a/artiq/gateware/targets/metlino.py
+++ b/artiq/gateware/targets/metlino.py
@@ -1,8 +1,10 @@
 #!/usr/bin/env python3
 
 import argparse
+from functools import partial
 
 from migen import *
+from migen.build.generic_platform import IOStandard
 
 from misoc.cores import gpio
 from misoc.integration.builder import builder_args, builder_argdict
@@ -126,12 +128,13 @@ class Master(MiniSoC, AMPSoC):
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
-                        iostandard="LVDS")
-        eem.Urukul.add_std(self, 0, 1, ttl_simple.Output,
-                           iostandard="LVDS")
-        eem.Zotino.add_std(self, 3, ttl_simple.Output,
-                           iostandard="LVDS")
+        output_4x = partial(ttl_serdes_ultrascale.Output, 4)
+        eem.DIO.add_std(self, 2, output_4x, output_4x,
+                        iostandard=lambda eem: IOStandard("LVDS"))
+        eem.Urukul.add_std(self, 0, 1, output_4x,
+                           iostandard=lambda eem: IOStandard("LVDS"))
+        eem.Zotino.add_std(self, 3, output_4x,
+                           iostandard=lambda eem: IOStandard("LVDS"))
         workaround_us_lvds_tristate(platform)
 
         self.config["HAS_RTIO_LOG"] = None
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 4edfc72c7..f46942e67 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -3,8 +3,10 @@
 import argparse
 import os
 import warnings
+from functools import partial
 
 from migen import *
+from migen.build.generic_platform import IOStandard
 
 from misoc.cores import gpio
 from misoc.integration.builder import builder_args, builder_argdict
@@ -349,10 +351,13 @@ class Satellite(SatelliteBase):
 
         # FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs)
         platform.add_connectors(fmcdio_vhdci_eem.connectors)
+        output_4x = partial(ttl_serdes_ultrascale.Output, 4)
         eem.DIO.add_std(self, 0,
-            ttl_simple.Output, ttl_simple.Output, iostandard="LVDS")
+            output_4x, output_4x,
+            iostandard=lambda eem: IOStandard("LVDS"))
         eem.DIO.add_std(self, 1,
-            ttl_simple.Output, ttl_simple.Output, iostandard="LVDS")
+            output_4x, output_4x,
+            iostandard=lambda eem: IOStandard("LVDS"))
         # FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3
         platform.add_extension(fmcdio_vhdci_eem.io)
         print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}"