forked from M-Labs/artiq
drtio: fix FullMemoryWE usage
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@ -205,14 +205,15 @@ class Receiver(Module, AutoCSR):
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)
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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class AuxController(Module):
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def __init__(self, link_layer):
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self.bus = wishbone.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
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# TODO: FullMemoryWE should be applied by migen.build
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tx_sdram_if = FullMemoryWE()(wishbone.SRAM(self.transmitter.mem, read_only=False))
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tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.bus.dat_w)//8)
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decoder = wishbone.Decoder(self.bus,
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