From e5286c57ab1582924a1e00ae2325df6a9e53b6d6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 30 Nov 2014 12:12:35 +0800 Subject: [PATCH] rtio: fix input FIFO depth config --- soc/artiqlib/rtio/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/artiqlib/rtio/core.py b/soc/artiqlib/rtio/core.py index 96938c23d..d173222af 100644 --- a/soc/artiqlib/rtio/core.py +++ b/soc/artiqlib/rtio/core.py @@ -286,7 +286,7 @@ class RTIO(Module, AutoCSR): self.submodules.bank_o = _RTIOBankO( phy.rbus, self.counter, fine_ts_width, ofifo_depth, guard_io_cycles) self.submodules.bank_i = _RTIOBankI( - phy.rbus, self.counter, fine_ts_width, ofifo_depth) + phy.rbus, self.counter, fine_ts_width, ififo_depth) # CSRs self._r_reset = CSRStorage(reset=1)