diff --git a/artiq/gateware/test/dsp/test_sawg.py b/artiq/gateware/test/dsp/test_sawg.py
index a5eea31bd..fd392607d 100644
--- a/artiq/gateware/test/dsp/test_sawg.py
+++ b/artiq/gateware/test/dsp/test_sawg.py
@@ -4,7 +4,7 @@ from migen import *
 from migen.fhdl.verilog import convert
 
 from artiq.gateware.dsp import sawg
-from .tools import xfer
+from artiq.gateware.test.dsp.tools import xfer
 
 
 def _test_gen_dds(dut, o):