forked from M-Labs/artiq
artiq/coredevice/dds: fix dds_set signature
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@ -24,7 +24,7 @@ def dds_batch_exit() -> TNone:
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@syscall
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def dds_set(time_mu: TInt64, channel: TInt32, ftw: TInt32,
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pow: TInt32, phase_mode: TInt32) -> TNone:
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pow: TInt32, phase_mode: TInt32, amplitude: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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