From e480bbe8d8c24e9c881d102917ccd95f558320b1 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Wed, 18 Oct 2023 13:02:54 +0800
Subject: [PATCH] artiq_ddb_template: move satellite_cpu_target to core

---
 artiq/coredevice/core.py             | 6 ++++--
 artiq/frontend/artiq_ddb_template.py | 8 +++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py
index f5a872335..ca9123bee 100644
--- a/artiq/coredevice/core.py
+++ b/artiq/coredevice/core.py
@@ -84,9 +84,11 @@ class Core:
         "core", "ref_period", "coarse_ref_period", "ref_multiplier",
     }
 
-    def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"):
+    def __init__(self, dmgr, host, ref_period, ref_multiplier=8, 
+                 target="rv32g", satellite_cpu_targets={}):
         self.ref_period = ref_period
         self.ref_multiplier = ref_multiplier
+        self.satellite_cpu_targets = satellite_cpu_targets
         self.target_cls = get_target_cls(target)
         self.coarse_ref_period = ref_period*ref_multiplier
         if host is None:
@@ -159,7 +161,7 @@ class Core:
                 if subkernel_args[0][0] == 'self':
                     self_arg = args[:1]
             destination = subkernel_fn.artiq_embedded.destination
-            destination_tgt = self.dmgr.ddb.get_satellite_cpu_target(destination)
+            destination_tgt = self.satellite_cpu_targets[destination]
             target = get_target_cls(destination_tgt)(subkernel_id=sid)
             object_map, kernel_library, _, _, _ = \
                 self.compile(subkernel_fn, self_arg, {}, attribute_writeback=False,
diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py
index a3272b5d5..394252911 100755
--- a/artiq/frontend/artiq_ddb_template.py
+++ b/artiq/frontend/artiq_ddb_template.py
@@ -34,7 +34,7 @@ def process_header(output, description):
                 "type": "local",
                 "module": "artiq.coredevice.core",
                 "class": "Core",
-                "arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}"}},
+                "arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}", "satellite_cpu_targets": {{}} }},
             }},
             "core_log": {{
                 "type": "controller",
@@ -60,8 +60,6 @@ def process_header(output, description):
                 "class": "CoreDMA"
             }},
 
-            "satellite_cpu_targets": {{}},
-
             "i2c_switch0": {{
                 "type": "local",
                 "module": "artiq.coredevice.i2c",
@@ -760,7 +758,7 @@ def process(output, primary_description, satellites):
         print(textwrap.dedent("""
             # DEST#{dest} peripherals
 
-            device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
+            device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
                 dest=destination,
                 target=get_cpu_target(description)),
             file=output)
@@ -773,7 +771,7 @@ def process(output, primary_description, satellites):
         print(textwrap.dedent("""
             # DEST#{dest} peripherals
 
-            device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
+            device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
                 dest=peripheral["drtio_destination"],
                 target=get_cpu_target(peripheral)),
             file=output)