forked from M-Labs/artiq
artiq_ddb_template: move satellite_cpu_target to core
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b168f0bb4b
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e480bbe8d8
@ -84,9 +84,11 @@ class Core:
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"core", "ref_period", "coarse_ref_period", "ref_multiplier",
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}
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def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"):
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def __init__(self, dmgr, host, ref_period, ref_multiplier=8,
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target="rv32g", satellite_cpu_targets={}):
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self.ref_period = ref_period
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self.ref_multiplier = ref_multiplier
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self.satellite_cpu_targets = satellite_cpu_targets
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self.target_cls = get_target_cls(target)
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self.coarse_ref_period = ref_period*ref_multiplier
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if host is None:
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@ -159,7 +161,7 @@ class Core:
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if subkernel_args[0][0] == 'self':
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self_arg = args[:1]
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destination = subkernel_fn.artiq_embedded.destination
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destination_tgt = self.dmgr.ddb.get_satellite_cpu_target(destination)
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destination_tgt = self.satellite_cpu_targets[destination]
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target = get_target_cls(destination_tgt)(subkernel_id=sid)
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object_map, kernel_library, _, _, _ = \
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self.compile(subkernel_fn, self_arg, {}, attribute_writeback=False,
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@ -34,7 +34,7 @@ def process_header(output, description):
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}"}},
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"arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}", "satellite_cpu_targets": {{}} }},
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}},
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"core_log": {{
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"type": "controller",
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@ -60,8 +60,6 @@ def process_header(output, description):
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"class": "CoreDMA"
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}},
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"satellite_cpu_targets": {{}},
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"i2c_switch0": {{
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"type": "local",
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"module": "artiq.coredevice.i2c",
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@ -760,7 +758,7 @@ def process(output, primary_description, satellites):
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print(textwrap.dedent("""
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# DEST#{dest} peripherals
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device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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dest=destination,
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target=get_cpu_target(description)),
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file=output)
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@ -773,7 +771,7 @@ def process(output, primary_description, satellites):
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print(textwrap.dedent("""
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# DEST#{dest} peripherals
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device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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dest=peripheral["drtio_destination"],
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target=get_cpu_target(peripheral)),
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file=output)
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