forked from M-Labs/artiq
firmware: Explicitly use wrapping integer math in PRNGs
Patch by Hannah McLaughlin; apparently, the overflow actually doesn't get checked/reported without `opt-level = 2` and `lto = "thin"`.
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@ -65,8 +65,8 @@ fn memory_test(total: &mut usize, wrong: &mut usize) -> bool {
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})
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})
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}
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}
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fn prng32(seed: &mut u32) -> u32 { *seed = 1664525 * *seed + 1013904223; *seed }
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fn prng32(seed: &mut u32) -> u32 { *seed = u32::wrapping_add(u32::wrapping_mul(1664525, *seed), 1013904223); *seed }
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fn prng16(seed: &mut u16) -> u16 { *seed = 25173 * *seed + 13849; *seed }
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fn prng16(seed: &mut u16) -> u16 { *seed = u16::wrapping_add(u16::wrapping_mul(25173, *seed), 13849); *seed }
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for _ in 0..4 {
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for _ in 0..4 {
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// Test data bus
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// Test data bus
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@ -211,9 +211,10 @@ mod ddr {
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// Generate pseudo-random sequence
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// Generate pseudo-random sequence
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let mut prs = [0; DFII_NPHASES * DFII_PIX_DATA_SIZE];
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let mut prs = [0; DFII_NPHASES * DFII_PIX_DATA_SIZE];
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let mut prv = 42;
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let mut prv: u32 = 42;
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for b in prs.iter_mut() {
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for b in prs.iter_mut() {
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prv = 1664525 * prv + 1013904223;
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prv = u32::wrapping_add(u32::wrapping_mul(1664525, prv), 1013904223);
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*b = prv as u8;
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*b = prv as u8;
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}
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}
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@ -296,7 +297,7 @@ mod ddr {
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let mut prs = [0; DFII_NPHASES * DFII_PIX_DATA_SIZE];
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let mut prs = [0; DFII_NPHASES * DFII_PIX_DATA_SIZE];
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let mut prv = 42;
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let mut prv = 42;
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for b in prs.iter_mut() {
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for b in prs.iter_mut() {
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prv = 1664525 * prv + 1013904223;
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prv = u32::wrapping_add(u32::wrapping_mul(1664525, prv), 1013904223);
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*b = prv as u8;
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*b = prv as u8;
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}
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}
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