srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

phaser: add two more registers before jesd

This commit is contained in:
Robert Jördens 2016-10-14 09:54:56 +02:00
parent 3c9c42c779
commit e400f8d672
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/gateware/targets/kc705.py
View File

@ -511,10 +511,11 @@ class AD9154(Module, AutoCSR):
x = Signal()
y = Signal()
self.sync.jesd += x.eq(~x)
z = Signal()
self.sync.jesd += x.eq(~x), z.eq(x == y)
self.sync.rio_phy += y.eq(x)
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
self.comb += conv.eq(Mux(x != y, Cat(ch.o[:2]), Cat(ch.o[2:])))
self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:])))
class Phaser(_NIST_Ions):