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urukul: ad9910 examples

This commit is contained in:
Robert Jördens 2018-01-03 18:42:58 +00:00
parent eae7584432
commit e3d66d286d
2 changed files with 77 additions and 28 deletions

View File

@ -237,7 +237,7 @@ device_db = {
"refclk": 100e6 "refclk": 100e6
} }
}, },
"urukul_ch0": { "urukul_ch0a": {
"type": "local", "type": "local",
"module": "artiq.coredevice.ad9912", "module": "artiq.coredevice.ad9912",
"class": "AD9912", "class": "AD9912",
@ -248,7 +248,7 @@ device_db = {
"sw_device": "ttl_urukul_sw0" "sw_device": "ttl_urukul_sw0"
} }
}, },
"urukul_ch1": { "urukul_ch1a": {
"type": "local", "type": "local",
"module": "artiq.coredevice.ad9912", "module": "artiq.coredevice.ad9912",
"class": "AD9912", "class": "AD9912",
@ -259,7 +259,7 @@ device_db = {
"sw_device": "ttl_urukul_sw1" "sw_device": "ttl_urukul_sw1"
} }
}, },
"urukul_ch2": { "urukul_ch2a": {
"type": "local", "type": "local",
"module": "artiq.coredevice.ad9912", "module": "artiq.coredevice.ad9912",
"class": "AD9912", "class": "AD9912",
@ -270,7 +270,7 @@ device_db = {
"sw_device": "ttl_urukul_sw2" "sw_device": "ttl_urukul_sw2"
} }
}, },
"urukul_ch3": { "urukul_ch3a": {
"type": "local", "type": "local",
"module": "artiq.coredevice.ad9912", "module": "artiq.coredevice.ad9912",
"class": "AD9912", "class": "AD9912",
@ -281,6 +281,50 @@ device_db = {
"sw_device": "ttl_urukul_sw3" "sw_device": "ttl_urukul_sw3"
} }
}, },
"urukul_ch0b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 4,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw0"
}
},
"urukul_ch1b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 5,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw1"
}
},
"urukul_ch2b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 6,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw2"
}
},
"urukul_ch3b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 7,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw3"
}
},
# AD9914 DDS # AD9914 DDS
"dds0": { "dds0": {

View File

@ -6,10 +6,14 @@ class UrukulTest(EnvExperiment):
self.setattr_device("core") self.setattr_device("core")
self.setattr_device("fmcdio_dirctl") self.setattr_device("fmcdio_dirctl")
self.setattr_device("urukul_cpld") self.setattr_device("urukul_cpld")
self.setattr_device("urukul_ch0") self.setattr_device("urukul_ch0a")
self.setattr_device("urukul_ch1") self.setattr_device("urukul_ch1a")
self.setattr_device("urukul_ch2") self.setattr_device("urukul_ch2a")
self.setattr_device("urukul_ch3") self.setattr_device("urukul_ch3a")
self.setattr_device("urukul_ch0b")
self.setattr_device("urukul_ch1b")
self.setattr_device("urukul_ch2b")
self.setattr_device("urukul_ch3b")
self.setattr_device("led") self.setattr_device("led")
def p(self, f, *a): def p(self, f, *a):
@ -25,36 +29,37 @@ class UrukulTest(EnvExperiment):
self.led.off() self.led.off()
self.urukul_cpld.init(clk_sel=1) self.urukul_cpld.init(clk_sel=1)
self.urukul_ch0.init() delay(1*ms) # DDS wake up
self.urukul_ch1.init() self.urukul_ch0b.init()
self.urukul_ch2.init() self.urukul_ch1b.init()
self.urukul_ch3.init() self.urukul_ch2b.init()
delay(100*us) self.urukul_ch3b.init()
self.urukul_ch0.set(10*MHz)
self.urukul_ch0.sw.on()
self.urukul_ch0.set_att(10.)
delay(100*us) delay(100*us)
self.urukul_ch1.set(10*MHz, 0.5) self.urukul_ch0b.set(100*MHz)
self.urukul_ch1.sw.on() self.urukul_ch0b.sw.on()
self.urukul_ch1.set_att(10.) self.urukul_ch0b.set_att(10.)
delay(100*us) delay(100*us)
self.urukul_ch2.set(400*MHz) self.urukul_ch1b.set(10*MHz, 0.5)
self.urukul_ch2.sw.on() self.urukul_ch1b.sw.on()
self.urukul_ch2.set_att(0.) self.urukul_ch1b.set_att(0.)
delay(100*us) delay(100*us)
self.urukul_ch3.set(1*MHz) self.urukul_ch2b.set(400*MHz)
self.urukul_ch3.sw.on() self.urukul_ch2b.sw.on()
self.urukul_ch3.set_att(0.) self.urukul_ch2b.set_att(0.)
delay(100*us)
self.urukul_ch3b.set(1*MHz)
self.urukul_ch3b.sw.on()
self.urukul_ch3b.set_att(20.)
while True: while True:
self.urukul_ch0.set_mu(0x123456789abc, 0) self.urukul_ch0b.set_mu(0x12345678, 0, 0x3fff)
while True: while True:
self.urukul_ch0.sw.pulse(5*ms) self.urukul_ch0b.sw.pulse(5*ms)
delay(5*ms) delay(5*ms)
while False: while False: