forked from M-Labs/artiq
ttl_simple: support differential io
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parent
956098c213
commit
e356150ac4
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@ -1,13 +1,15 @@
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from migen import *
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialInput, DifferentialOutput
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio import rtlink
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class Output(Module):
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class Output(Module):
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def __init__(self, pad):
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def __init__(self, pad, pad_n=None):
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self.rtlink = rtlink.Interface(rtlink.OInterface(1))
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self.rtlink = rtlink.Interface(rtlink.OInterface(1))
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self.probes = [pad]
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pad_o = Signal(reset_less=True)
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self.probes = [pad_o]
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override_en = Signal()
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override_en = Signal()
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override_o = Signal()
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override_o = Signal()
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self.overrides = [override_en, override_o]
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self.overrides = [override_en, override_o]
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@ -20,15 +22,19 @@ class Output(Module):
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pad_k.eq(self.rtlink.o.data)
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pad_k.eq(self.rtlink.o.data)
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),
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),
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If(override_en,
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If(override_en,
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pad.eq(override_o)
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pad_o.eq(override_o)
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).Else(
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).Else(
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pad.eq(pad_k)
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pad_o.eq(pad_k)
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)
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)
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]
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]
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if pad_n is None:
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self.comb += pad.eq(pad_o)
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else:
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self.specials += DifferentialOutput(pad_o, pad, pad_n)
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class Input(Module):
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class Input(Module):
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def __init__(self, pad):
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def __init__(self, pad, pad_n=None):
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self.rtlink = rtlink.Interface(
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(2, 2),
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rtlink.OInterface(2, 2),
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rtlink.IInterface(1))
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rtlink.IInterface(1))
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@ -49,8 +55,13 @@ class Input(Module):
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]
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]
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i = Signal()
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i = Signal()
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i_d = Signal()
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i_d = Signal(reset_less=True)
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self.specials += MultiReg(pad, i, "rio_phy")
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pad_i = Signal()
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if pad_n is None:
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self.comb += pad_i.eq(pad)
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else:
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self.specials += DifferentialInput(pad, pad_n, pad_i)
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self.specials += MultiReg(pad_i, i, "rio_phy")
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self.sync.rio_phy += i_d.eq(i)
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self.sync.rio_phy += i_d.eq(i)
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self.comb += [
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self.comb += [
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self.rtlink.i.stb.eq(
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self.rtlink.i.stb.eq(
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