forked from M-Labs/artiq
pcu: refactor into a device
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b05d1bb7e3
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e323e37829
@ -31,8 +31,13 @@ def _PCMR(n):
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return _SPRGROUP_PC + 8 + n
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class CorePCU:
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"""Core device performance counter unit (PCU) access"""
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def __init__(self, dmgr, core_device="core"):
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self.core = dmgr.get(core_device)
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@kernel
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def pc_start():
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def start(self):
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"""
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Configure and clear the kernel CPU performance counters.
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@ -60,11 +65,11 @@ def pc_start():
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mtspr(_PCMR(6), _SPR_PCMR_CISM | _SPR_PCMR_BS)
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mtspr(_PCMR(7), _SPR_PCMR_CISM | _SPR_PCMR_DDS)
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@kernel
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def pc_get(r):
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def get(self, r):
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"""
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Read the performance counters and store the counts in the array provided.
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Read the performance counters and store the counts in the
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array provided.
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:param list[int] r: array to store the counter values
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"""
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