forked from M-Labs/artiq
firmware/i2c: rewrite I2C implementation
* Never drive SDL or SDA high. They are specified to be open collector/drain and pulled up by resistive pullups. Driving high fails miserably in a multi-master topology (e.g. with a USB I2C interface). It would only ever be implemented to speed up the bus actively but that's tricky and completely unnecessary here. * Make the handover states between the I2C protocol phases (start, stop, restart, write, read) well defined. Add comments stressing those pre/postconditions. * Add checks for SDA arbitration failures and stuck SCL. * Remove wrong, misleading or redundant comments.
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@ -14,6 +14,12 @@ mod imp {
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}
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}
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fn scl_i(busno: u8) -> bool {
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unsafe {
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csr::i2c::in_read() & scl_bit(busno) != 0
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}
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}
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fn sda_oe(busno: u8, oe: bool) {
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unsafe {
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let reg = csr::i2c::oe_read();
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@ -49,13 +55,10 @@ mod imp {
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pub fn init() -> Result<(), &'static str> {
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for busno in 0..csr::CONFIG_I2C_BUS_COUNT {
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let busno = busno as u8;
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// Set SCL as output, and high level
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scl_o(busno, true);
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scl_oe(busno, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(busno, false);
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// Release SDA
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scl_oe(busno, false);
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sda_oe(busno, false);
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scl_o(busno, false);
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sda_o(busno, false);
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// Check the I2C bus is ready
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half_period();
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@ -63,9 +66,9 @@ mod imp {
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if !sda_i(busno) {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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scl_o(busno, false);
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scl_oe(busno, true);
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half_period();
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scl_o(busno, true);
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scl_oe(busno, false);
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half_period();
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}
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}
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@ -73,6 +76,10 @@ mod imp {
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if !sda_i(busno) {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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if !scl_i(busno) {
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return Err("SCL is stuck low and doesn't get unstuck");
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}
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// postcondition: SCL and SDA high
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}
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Ok(())
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}
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@ -81,11 +88,17 @@ mod imp {
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if busno as u32 >= csr::CONFIG_I2C_BUS_COUNT {
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return Err(INVALID_BUS)
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}
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// Set SCL high then SDA low
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scl_o(busno, true);
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half_period();
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// precondition: SCL and SDA high
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if !scl_i(busno) {
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return Err("SCL is stuck low and doesn't get unstuck");
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}
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if !sda_i(busno) {
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return Err("SDA arbitration lost");
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}
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sda_oe(busno, true);
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half_period();
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scl_oe(busno, true);
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// postcondition: SCL and SDA low
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Ok(())
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}
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@ -93,13 +106,13 @@ mod imp {
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if busno as u32 >= csr::CONFIG_I2C_BUS_COUNT {
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return Err(INVALID_BUS)
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}
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// Set SCL low then SDA high */
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scl_o(busno, false);
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half_period();
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// precondition SCL and SDA low
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sda_oe(busno, false);
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half_period();
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// Do a regular start
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scl_oe(busno, false);
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half_period();
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start(busno)?;
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// postcondition: SCL and SDA low
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Ok(())
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}
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@ -107,15 +120,16 @@ mod imp {
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if busno as u32 >= csr::CONFIG_I2C_BUS_COUNT {
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return Err(INVALID_BUS)
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}
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(busno, false);
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// precondition: SCL and SDA low
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half_period();
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// Set SCL high then SDA high
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sda_oe(busno, true);
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scl_o(busno, true);
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scl_oe(busno, false);
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half_period();
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sda_oe(busno, false);
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half_period();
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if !sda_i(busno) {
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return Err("SDA arbitration lost");
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}
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// postcondition: SCL and SDA high
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Ok(())
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}
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@ -123,57 +137,53 @@ mod imp {
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if busno as u32 >= csr::CONFIG_I2C_BUS_COUNT {
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return Err(INVALID_BUS)
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}
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// precondition: SCL and SDA low
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(busno, false);
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sda_oe(busno, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(busno, true);
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scl_oe(busno, false);
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half_period();
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scl_oe(busno, true);
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(busno, false);
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half_period();
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sda_oe(busno, false);
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// Set SCL high and check for ack
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scl_o(busno, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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Ok(!sda_i(busno))
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scl_oe(busno, false);
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half_period();
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// Read ack/nack
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let ack = !sda_i(busno);
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scl_oe(busno, true);
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sda_oe(busno, true);
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// postcondition: SCL and SDA low
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Ok(ack)
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}
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pub fn read(busno: u8, ack: bool) -> Result<u8, &'static str> {
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if busno as u32 >= csr::CONFIG_I2C_BUS_COUNT {
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return Err(INVALID_BUS)
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}
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(busno, false);
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half_period(); // make sure SCL has settled low
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// precondition: SCL and SDA low
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sda_oe(busno, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(busno, false);
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half_period();
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// Set SCL high and shift data
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scl_o(busno, true);
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scl_oe(busno, false);
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half_period();
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if sda_i(busno) { data |= 1 << bit }
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scl_oe(busno, true);
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(busno, false);
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if ack { sda_oe(busno, true) }
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// Send ack/nack
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sda_oe(busno, ack);
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half_period();
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// then set SCL high
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scl_o(busno, true);
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scl_oe(busno, false);
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half_period();
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scl_oe(busno, true);
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sda_oe(busno, true);
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// postcondition: SCL and SDA low
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Ok(data)
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}
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