forked from M-Labs/artiq
rtio/sed: trigger collision error on non-data replace
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parent
770ce2658f
commit
e2c1d4f3d5
@ -29,7 +29,10 @@ class Gates(Module):
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else:
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self.sync += getattr(output.payload, field).eq(getattr(input.payload, field))
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self.sync += output.seqn.eq(input.seqn)
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self.comb += output.replace_occured.eq(0)
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self.comb += [
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output.replace_occured.eq(0),
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output.nondata_replace_occured.eq(0)
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]
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self.comb += input.re.eq(input.payload.timestamp[fine_ts_width:] == self.coarse_timestamp)
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self.sync += output.valid.eq(input.re & input.readable)
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@ -69,5 +69,6 @@ def output_network_node(seqn_width, layout_payload):
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("valid", 1),
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("seqn", seqn_width),
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("replace_occured", 1),
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("nondata_replace_occured", 1),
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("payload", layout_payload)
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]
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@ -33,10 +33,12 @@ class OutputDriver(Module):
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en_replaces = [channel.interface.o.enable_replace for channel in channels]
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for lane_data, on_output in zip(lane_datas, output_network.output):
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replace_occured_r = Signal()
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nondata_replace_occured_r = Signal()
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self.sync += [
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lane_data.valid.eq(on_output.valid),
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lane_data.payload.eq(on_output.payload),
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replace_occured_r.eq(on_output.replace_occured),
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nondata_replace_occured_r.eq(on_output.nondata_replace_occured)
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]
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en_replaces_rom = Memory(1, len(en_replaces), init=en_replaces)
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@ -44,7 +46,7 @@ class OutputDriver(Module):
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self.specials += en_replaces_rom, en_replaces_rom_port
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self.comb += [
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en_replaces_rom_port.adr.eq(on_output.payload.channel),
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lane_data.collision.eq(replace_occured_r & ~en_replaces_rom_port.dat_r)
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lane_data.collision.eq(replace_occured_r & (~en_replaces_rom_port.dat_r | nondata_replace_occured_r))
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]
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self.sync += [
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@ -60,6 +60,13 @@ class OutputNetwork(Module):
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for _ in range(lane_count)]
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for node1, node2 in step:
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nondata_difference = Signal()
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for field, _ in layout_payload:
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if field != "data":
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f1 = getattr(step_input[node1].payload, field)
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f2 = getattr(step_input[node2].payload, field)
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self.comb += If(f1 != f2, nondata_difference.eq(1))
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k1 = Cat(step_input[node1].payload.channel, ~step_input[node1].valid)
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k2 = Cat(step_input[node2].payload.channel, ~step_input[node2].valid)
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self.sync += [
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@ -72,6 +79,7 @@ class OutputNetwork(Module):
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step_output[node2].eq(step_input[node2])
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),
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step_output[node1].replace_occured.eq(1),
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step_output[node1].nondata_replace_occured.eq(nondata_difference),
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step_output[node2].valid.eq(0),
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).Elif(k1 < k2,
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step_output[node1].eq(step_input[node1]),
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