From e229edd5d554e637f2871371b99f658ddb62c030 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Mon, 12 Jun 2017 23:08:27 +0200
Subject: [PATCH] sawg: add register after hbf for timing

---
 artiq/gateware/dsp/sawg.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py
index af0e03c0c..290609bb4 100644
--- a/artiq/gateware/dsp/sawg.py
+++ b/artiq/gateware/dsp/sawg.py
@@ -172,7 +172,7 @@ class Channel(Module, SatAddMixin):
             Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
         ]
         for i in range(parallelism):
-            self.comb += [
+            self.sync += [
                 b.xi[i].eq(self.sat_add(hbf[0].o[i],
                                      limits=cfg.limits[0],
                                      clipped=cfg.clipped[0])),