srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

phaser: tweak docs, relax slack

This commit is contained in:
Robert Jördens 2022-10-19 16:42:03 +02:00
parent 1820e1f715
commit e15b5b50d8
1 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
artiq/coredevice/phaser.py
View File

@ -89,8 +89,8 @@ class Phaser:
quadrature modulation compensation and interpolation features. quadrature modulation compensation and interpolation features.
The coredevice RTIO PHY and the Phaser gateware come in different modes The coredevice RTIO PHY and the Phaser gateware come in different modes
that have different features. Phaser mode and coredevice PHY are both that have different features. Phaser mode and coredevice PHY mode are both
both selected at gateware compile-time and need to match. selected at their respective gateware compile-time and need to match.
=============== ============== =================================== =============== ============== ===================================
Phaser gateware Coredevice PHY Features per :class:`PhaserChannel` Phaser gateware Coredevice PHY Features per :class:`PhaserChannel`
@ -100,6 +100,12 @@ class Phaser:
Miqro >= v0.6 Miqro :class:`Miqro` Miqro >= v0.6 Miqro :class:`Miqro`
=============== ============== =================================== =============== ============== ===================================
The coredevice driver (this class and :class:`PhaserChannel`) exposes
the superset of all functionality regardless of the Coredevice RTIO PHY
or Phaser gateware modes. This is to evade type unification limitations.
Features absent in Coredevice PHY/Phaser gateware will not work and
should not be accessed.
**Base mode** **Base mode**
The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25 The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
@ -833,8 +839,9 @@ class PhaserChannel:
A Phaser channel contains: A Phaser channel contains:
* multiple oscillators (in the coredevice phy), * multiple :class:`PhaserOscillator` (in the coredevice phy),
* an interpolation chain and digital upconverter (DUC) on Phaser, * an interpolation chain and digital upconverter (DUC) on Phaser,
* a :class:`Miqro` instance on Phaser,
* several channel-specific settings in the DAC: * several channel-specific settings in the DAC:
* quadrature modulation compensation QMC * quadrature modulation compensation QMC
@ -846,6 +853,7 @@ class PhaserChannel:
Attributes: Attributes:
* :attr:`oscillator`: List of five :class:`PhaserOscillator`. * :attr:`oscillator`: List of five :class:`PhaserOscillator`.
* :attr:`miqro`: A :class:`Miqro`.
.. note:: The amplitude sum of the oscillators must be less than one to .. note:: The amplitude sum of the oscillators must be less than one to
avoid clipping or overflow. If any of the DDS or DUC frequencies are avoid clipping or overflow. If any of the DDS or DUC frequencies are
@ -858,6 +866,8 @@ class PhaserChannel:
changes in oscillator parameters, the overshoot can lead to clipping changes in oscillator parameters, the overshoot can lead to clipping
or overflow after the interpolation. Either band-limit any changes or overflow after the interpolation. Either band-limit any changes
in the oscillator parameters or back off the amplitude sufficiently. in the oscillator parameters or back off the amplitude sufficiently.
Miqro is not affected by this. But both the oscillators and Miqro can
be affected by intrinsic overshoot of the interpolator on the DAC.
""" """
kernel_invariants = {"index", "phaser", "trf_mmap"} kernel_invariants = {"index", "phaser", "trf_mmap"}
@ -1422,7 +1432,7 @@ class Miqro:
""" """
for osc in range(16): for osc in range(16):
self.set_profile_mu(osc, profile=0, ftw=0, asf=0) self.set_profile_mu(osc, profile=0, ftw=0, asf=0)
delay(10*us) delay(20*us)
self.set_window_mu(start=0, iq=[0], order=0) self.set_window_mu(start=0, iq=[0], order=0)
self.pulse(window=0, profiles=[0]) self.pulse(window=0, profiles=[0])
@ -1512,7 +1522,7 @@ class Miqro:
) )
for iqi in iq: for iqi in iq:
self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA, iqi) self.channel.phaser.write32(PHASER_ADDR_MIQRO_MEM_DATA, iqi)
delay(10*us) # slack for long windows delay(20*us) # slack for long windows
return (start + 1 + len(iq)) & 0x3ff return (start + 1 + len(iq)) & 0x3ff
@kernel @kernel