forked from M-Labs/artiq
sayma_amc: constrain pin, remove keep
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ee14912042
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@ -55,6 +55,7 @@ class AD9154CRG(Module, AutoCSR):
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b00,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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@ -62,8 +63,6 @@ class AD9154CRG(Module, AutoCSR):
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Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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self.cd_jesd.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/self.refclk_freq)
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jref = platform.request("dac_sysref")
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self.specials += DifferentialInput(jref.p, jref.n, self.jref)
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@ -85,7 +84,6 @@ class AD9154JESD(Module, AutoCSR):
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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phy.transmitter.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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