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serwb: remove idelaye3 en_vtc (was not done correctly, we'll add direct software control)

This commit is contained in:
Florent Kermarrec 2018-05-12 01:32:16 +02:00
parent 6b4bbe31f7
commit e09dbc89bc
2 changed files with 1 additions and 6 deletions
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3
artiq/gateware/serwb/kusphy.py
View File

@ -32,7 +32,6 @@ class KUSSerdes(Module):
self.rx_bitslip_value = Signal(6) self.rx_bitslip_value = Signal(6)
self.rx_delay_rst = Signal() self.rx_delay_rst = Signal()
self.rx_delay_inc = Signal() self.rx_delay_inc = Signal()
self.rx_delay_en_vtc = Signal()
# # # # # #
@ -174,7 +173,7 @@ class KUSSerdes(Module):
i_CLK=ClockSignal("sys"), i_CLK=ClockSignal("sys"),
i_RST=self.rx_delay_rst, i_LOAD=0, i_RST=self.rx_delay_rst, i_LOAD=0,
i_INC=1, i_EN_VTC=self.rx_delay_en_vtc, i_INC=1, i_EN_VTC=0,
i_CE=self.rx_delay_inc, i_CE=self.rx_delay_inc,
i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed

4
artiq/gateware/serwb/phy.py
View File

@ -147,8 +147,6 @@ class _SerdesMasterInit(Module):
fsm.act("READY", fsm.act("READY",
self.ready.eq(1) self.ready.eq(1)
) )
if hasattr(serdes, "rx_delay_en_vtc"):
self.comb += serdes.rx_delay_en_vtc.eq(self.ready)
fsm.act("ERROR", fsm.act("ERROR",
self.error.eq(1) self.error.eq(1)
) )
@ -277,8 +275,6 @@ class _SerdesSlaveInit(Module, AutoCSR):
fsm.act("READY", fsm.act("READY",
self.ready.eq(1) self.ready.eq(1)
) )
if hasattr(serdes, "rx_delay_en_vtc"):
self.comb += serdes.rx_delay_en_vtc.eq(self.ready)
fsm.act("ERROR", fsm.act("ERROR",
self.error.eq(1) self.error.eq(1)
) )