diff --git a/artiq/gateware/serwb/kusphy.py b/artiq/gateware/serwb/kusphy.py
index 395c4c0b7..dd7cf6760 100644
--- a/artiq/gateware/serwb/kusphy.py
+++ b/artiq/gateware/serwb/kusphy.py
@@ -32,7 +32,6 @@ class KUSSerdes(Module):
         self.rx_bitslip_value = Signal(6)
         self.rx_delay_rst = Signal()
         self.rx_delay_inc = Signal()
-        self.rx_delay_en_vtc = Signal()
 
         # # #
 
@@ -174,7 +173,7 @@ class KUSSerdes(Module):
 
                 i_CLK=ClockSignal("sys"),
                 i_RST=self.rx_delay_rst, i_LOAD=0,
-                i_INC=1, i_EN_VTC=self.rx_delay_en_vtc,
+                i_INC=1, i_EN_VTC=0,
                 i_CE=self.rx_delay_inc,
 
                 i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed
diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py
index 8a921dbe6..de7c4144e 100644
--- a/artiq/gateware/serwb/phy.py
+++ b/artiq/gateware/serwb/phy.py
@@ -147,8 +147,6 @@ class _SerdesMasterInit(Module):
         fsm.act("READY",
             self.ready.eq(1)
         )
-        if hasattr(serdes, "rx_delay_en_vtc"):
-            self.comb += serdes.rx_delay_en_vtc.eq(self.ready)
         fsm.act("ERROR",
             self.error.eq(1)
         )
@@ -277,8 +275,6 @@ class _SerdesSlaveInit(Module, AutoCSR):
         fsm.act("READY",
             self.ready.eq(1)
         )
-        if hasattr(serdes, "rx_delay_en_vtc"):
-            self.comb += serdes.rx_delay_en_vtc.eq(self.ready)
         fsm.act("ERROR",
             self.error.eq(1)
         )