forked from M-Labs/artiq
wrpll: new collector from Weida/Tom
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dee16edb78
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dfa033eb87
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@ -79,6 +79,9 @@ class WRPLL(Module, AutoCSR):
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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collector_update = Signal()
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self.sync.helper += collector_update.eq(ddmtd_counter == (2**N - 1))
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filter_cd = ClockDomainsRenamer("filter")
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filter_cd = ClockDomainsRenamer("filter")
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self.submodules.collector = filter_cd(Collector(N))
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self.submodules.collector = filter_cd(Collector(N))
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self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48))
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self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48))
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@ -98,7 +101,7 @@ class WRPLL(Module, AutoCSR):
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]
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]
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self.comb += [
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self.comb += [
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self.filter_main.input.eq(self.collector.output),
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self.filter_main.input.eq(self.collector.output),
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self.filter_main.input_stb.eq(self.collector.output_update)
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self.filter_main.input_stb.eq(collector_update)
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]
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]
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self.sync.helper += [
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self.sync.helper += [
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@ -131,20 +131,19 @@ class DDMTD(Module, AutoCSR):
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class Collector(Module):
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class Collector(Module):
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def __init__(self, N):
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def __init__(self, N):
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self.tag_helper = Signal(N)
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self.tag_helper = Signal((N, True))
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self.tag_helper_update = Signal()
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self.tag_helper_update = Signal()
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self.tag_main = Signal(N)
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self.tag_main = Signal((N, True))
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self.tag_main_update = Signal()
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self.tag_main_update = Signal()
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self.output = Signal((N, True))
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self.output = Signal((N + 1, True))
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self.output_update = Signal(N)
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# # #
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# # #
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.submodules += fsm
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tag_collector = Signal(N)
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tag_collector = Signal((N + 1, True))
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fsm.act("IDLE",
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fsm.act("IDLE",
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If(self.tag_main_update & self.tag_helper_update,
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If(self.tag_main_update & self.tag_helper_update,
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NextValue(tag_collector, 0),
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NextValue(tag_collector, 0),
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@ -160,17 +159,32 @@ class Collector(Module):
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fsm.act("WAITHELPER",
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fsm.act("WAITHELPER",
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If(self.tag_helper_update,
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If(self.tag_helper_update,
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NextValue(tag_collector, tag_collector - self.tag_helper),
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NextValue(tag_collector, tag_collector - self.tag_helper),
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NextState("UPDATE")
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NextState("LEADCHECK")
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)
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)
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)
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)
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fsm.act("WAITMAIN",
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fsm.act("WAITMAIN",
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If(self.tag_main_update,
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If(self.tag_main_update,
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NextValue(tag_collector, tag_collector + self.tag_main),
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NextValue(tag_collector, tag_collector + self.tag_main),
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NextState("UPDATE")
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NextState("LAGCHECK")
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)
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)
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)
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)
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# To compensate DDMTD counter roll-over when main is ahead of roll-over
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# and helper is after roll-over
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fsm.act("LEADCHECK",
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If(tag_collector > 0,
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NextValue(tag_collector, tag_collector - (2**N - 1))
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),
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NextState("UPDATE")
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)
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# To compensate DDMTD counter roll-over when helper is ahead of roll-over
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# and main is after roll-over
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fsm.act("LAGCHECK",
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If(tag_collector < 0,
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NextValue(tag_collector, tag_collector + (2**N - 1))
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),
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NextState("UPDATE")
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)
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fsm.act("UPDATE",
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fsm.act("UPDATE",
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NextValue(self.output, tag_collector),
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NextValue(self.output, tag_collector),
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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self.sync += self.output_update.eq(self.tag_helper_update)
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