forked from M-Labs/artiq
coredevice/ad9912: port to NAC3
This commit is contained in:
parent
93f24c9f94
commit
df87cc88d6
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@ -1,14 +1,16 @@
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from numpy import int32, int64
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from artiq.language.types import TInt32, TInt64, TFloat, TTuple, TBool
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from artiq.language.core import kernel, delay, portable
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from artiq.language.core import KernelInvariant, nac3, kernel, portable
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from artiq.language.units import ms, us, ns
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from artiq.coredevice.ad9912_reg import *
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import urukul
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from artiq.coredevice.core import Core
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from artiq.coredevice.spi2 import *
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from artiq.coredevice.urukul import *
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from artiq.coredevice.ttl import TTLOut
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@nac3
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class AD9912:
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"""
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AD9912 DDS channel on Urukul
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@ -27,10 +29,16 @@ class AD9912:
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instance).
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"""
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core: KernelInvariant[Core]
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cpld: KernelInvariant[CPLD]
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bus: KernelInvariant[SPIMaster]
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chip_select: KernelInvariant[int32]
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pll_n: KernelInvariant[int32]
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ftw_per_hz: KernelInvariant[float]
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sw: KernelInvariant[TTLOut]
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=10):
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self.kernel_invariants = {"cpld", "core", "bus", "chip_select",
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"pll_n", "ftw_per_hz"}
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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@ -38,14 +46,13 @@ class AD9912:
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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self.pll_n = pll_n
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sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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assert sysclk <= 1e9
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self.ftw_per_hz = 1 / sysclk * (int64(1) << 48)
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self.ftw_per_hz = 1 / sysclk * (1 << 48)
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@kernel
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def write(self, addr: TInt32, data: TInt32, length: TInt32):
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def write(self, addr: int32, data: int32, length: int32):
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"""Variable length write to a register.
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Up to 4 bytes.
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@ -53,17 +60,17 @@ class AD9912:
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:param data: Data to be written: int32
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:param length: Length in bytes (1-4)
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"""
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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# NAC3TODO assert length > 0
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# NAC3TODO assert length <= 4
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self.bus.set_config_mu(SPI_CONFIG, 16,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13)) << 16)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, length * 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, length * 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(data << (32 - length * 8))
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@kernel
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def read(self, addr: TInt32, length: TInt32) -> TInt32:
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def read(self, addr: int32, length: int32) -> int32:
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"""Variable length read from a register.
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Up to 4 bytes.
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@ -71,18 +78,19 @@ class AD9912:
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:param length: Length in bytes (1-4)
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:return: Data read
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"""
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assert length > 0
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assert length <= 4
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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# NAC3TODO assert length > 0
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# NAC3TODO assert length <= 4
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self.bus.set_config_mu(SPI_CONFIG, 16,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END
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| spi.SPI_INPUT, length * 8,
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END
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| SPI_INPUT, length * 8,
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SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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data = self.bus.read()
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if length < 4:
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data &= (1 << (length * 8)) - 1
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# NAC3TODO data &= (1 << (length * 8)) - 1
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data = data & (1 << (length * 8)) - 1
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return data
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@kernel
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@ -94,25 +102,26 @@ class AD9912:
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IO_UPDATE signal multiple times.
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"""
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# SPI mode
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self.write(AD9912_SER_CONF, 0x99, length=1)
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self.cpld.io_update.pulse(2 * us)
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self.write(AD9912_SER_CONF, 0x99, 1)
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self.cpld.io_update.pulse(2. * us)
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# Verify chip ID and presence
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prodid = self.read(AD9912_PRODIDH, length=2)
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prodid = self.read(AD9912_PRODIDH, 2)
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if (prodid != 0x1982) and (prodid != 0x1902):
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raise ValueError("Urukul AD9912 product id mismatch")
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delay(50 * us)
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# NAC3TODO raise ValueError("Urukul AD9912 product id mismatch")
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pass
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self.core.delay(50. * us)
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# HSTL power down, CMOS power down
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self.write(AD9912_PWRCNTRL1, 0x80, length=1)
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self.cpld.io_update.pulse(2 * us)
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self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
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self.cpld.io_update.pulse(2 * us)
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self.write(AD9912_PWRCNTRL1, 0x80, 1)
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self.cpld.io_update.pulse(2. * us)
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self.write(AD9912_N_DIV, self.pll_n // 2 - 2, 1)
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self.cpld.io_update.pulse(2. * us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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self.cpld.io_update.pulse(2 * us)
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delay(1 * ms)
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self.write(AD9912_PLLCFG, 0b00000101, 1)
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self.cpld.io_update.pulse(2. * us)
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self.core.delay(1. * ms)
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@kernel
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def set_att_mu(self, att: TInt32):
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# NAC3TODO @kernel
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def set_att_mu(self, att: int32):
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"""Set digital step attenuator in machine units.
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This method will write the attenuator settings of all four channels.
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@ -123,8 +132,8 @@ class AD9912:
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"""
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self.cpld.set_att_mu(self.chip_select - 4, att)
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@kernel
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def set_att(self, att: TFloat):
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# NAC3TODO @kernel
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def set_att(self, att: float):
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"""Set digital step attenuator in SI units.
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This method will write the attenuator settings of all four channels.
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@ -136,7 +145,7 @@ class AD9912:
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self.cpld.set_att(self.chip_select - 4, att)
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@kernel
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def get_att_mu(self) -> TInt32:
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def get_att_mu(self) -> int32:
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"""Get digital step attenuator value in machine units.
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.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att_mu`
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@ -146,7 +155,7 @@ class AD9912:
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return self.cpld.get_channel_att_mu(self.chip_select - 4)
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@kernel
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def get_att(self) -> TFloat:
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def get_att(self) -> float:
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"""Get digital step attenuator value in SI units.
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.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att`
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@ -156,7 +165,7 @@ class AD9912:
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return self.cpld.get_channel_att(self.chip_select - 4)
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@kernel
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def set_mu(self, ftw: TInt64, pow_: TInt32):
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def set_mu(self, ftw: int64, pow_: int32):
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"""Set profile 0 data in machine units.
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After the SPI transfer, the shared IO update pin is pulsed to
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@ -166,19 +175,19 @@ class AD9912:
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:param pow_: Phase tuning word: 16 bit unsigned.
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"""
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# streaming transfer of FTW and POW
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self.bus.set_config_mu(urukul.SPI_CONFIG, 16,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 16,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((AD9912_POW1 << 16) | (3 << 29))
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((pow_ << 16) | (int32(ftw >> 32) & 0xffff))
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((pow_ << 16) | (int32(ftw >> int64(32)) & 0xffff))
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(int32(ftw))
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self.cpld.io_update.pulse(10 * ns)
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self.cpld.io_update.pulse(10. * ns)
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@kernel
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def get_mu(self) -> TTuple([TInt64, TInt32]):
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def get_mu(self) -> tuple[int64, int32]:
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"""Get the frequency tuning word and phase offset word.
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.. seealso:: :meth:`get`
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@ -191,34 +200,34 @@ class AD9912:
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self.core.break_realtime() # Regain slack to perform second read
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low = self.read(AD9912_FTW3, 4)
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# Extract and return fields
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ftw = (int64(high & 0xffff) << 32) | (int64(low) & int64(0xffffffff))
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ftw = (int64(high & 0xffff) << int64(32)) | (int64(low) & int64(0xffffffff))
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pow_ = (high >> 16) & 0x3fff
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return ftw, pow_
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@portable(flags={"fast-math"})
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def frequency_to_ftw(self, frequency: TFloat) -> TInt64:
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@portable
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def frequency_to_ftw(self, frequency: float) -> int64:
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"""Returns the 48-bit frequency tuning word corresponding to the given
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frequency.
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"""
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return int64(round(self.ftw_per_hz * frequency)) & (
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(int64(1) << 48) - 1)
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(int64(1) << int64(48)) - int64(1))
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@portable(flags={"fast-math"})
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def ftw_to_frequency(self, ftw: TInt64) -> TFloat:
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@portable
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def ftw_to_frequency(self, ftw: int64) -> float:
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"""Returns the frequency corresponding to the given
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frequency tuning word.
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"""
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return ftw / self.ftw_per_hz
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return float(ftw) / self.ftw_per_hz
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@portable(flags={"fast-math"})
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def turns_to_pow(self, phase: TFloat) -> TInt32:
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@portable
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def turns_to_pow(self, phase: float) -> int32:
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"""Returns the 16-bit phase offset word corresponding to the given
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phase.
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"""
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return int32(round((1 << 14) * phase)) & 0xffff
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return int32(round(float(1 << 14) * phase)) & 0xffff
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@portable(flags={"fast-math"})
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def pow_to_turns(self, pow_: TInt32) -> TFloat:
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@portable
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def pow_to_turns(self, pow_: int32) -> float:
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"""Return the phase in turns corresponding to a given phase offset
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word.
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@ -228,7 +237,7 @@ class AD9912:
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return pow_ / (1 << 14)
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@kernel
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def set(self, frequency: TFloat, phase: TFloat = 0.0):
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def set(self, frequency: float, phase: float = 0.0):
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"""Set profile 0 data in SI units.
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.. seealso:: :meth:`set_mu`
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@ -240,7 +249,7 @@ class AD9912:
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self.turns_to_pow(phase))
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@kernel
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def get(self) -> TTuple([TFloat, TFloat]):
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def get(self) -> tuple[float, float]:
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"""Get the frequency and phase.
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.. seealso:: :meth:`get_mu`
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@ -253,8 +262,8 @@ class AD9912:
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# Convert and return
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return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_)
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@kernel
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def cfg_sw(self, state: TBool):
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# NAC3TODO @kernel
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def cfg_sw(self, state: bool):
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"""Set CPLD CFG RF switch state. The RF switch is controlled by the
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logical or of the CPLD configuration shift register
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RF switch bit and the SW TTL line (if used).
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@ -1,78 +1,78 @@
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# auto-generated, do not edit
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from numpy import int32
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from artiq.language.core import portable
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from artiq.language.types import TInt32
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AD9912_SER_CONF = 0x000
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# default: 0x00, access: R/W
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@portable
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def AD9912_SDOACTIVE_SET(x: TInt32) -> TInt32:
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def AD9912_SDOACTIVE_SET(x: int32) -> int32:
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return (x & 0x1) << 0
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@portable
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def AD9912_SDOACTIVE_GET(x: TInt32) -> TInt32:
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def AD9912_SDOACTIVE_GET(x: int32) -> int32:
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return (x >> 0) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_LSBFIRST_SET(x: TInt32) -> TInt32:
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def AD9912_LSBFIRST_SET(x: int32) -> int32:
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return (x & 0x1) << 1
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@portable
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def AD9912_LSBFIRST_GET(x: TInt32) -> TInt32:
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def AD9912_LSBFIRST_GET(x: int32) -> int32:
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return (x >> 1) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SOFTRESET_SET(x: TInt32) -> TInt32:
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def AD9912_SOFTRESET_SET(x: int32) -> int32:
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return (x & 0x1) << 2
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@portable
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def AD9912_SOFTRESET_GET(x: TInt32) -> TInt32:
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def AD9912_SOFTRESET_GET(x: int32) -> int32:
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return (x >> 2) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_LONGINSN_SET(x: TInt32) -> TInt32:
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def AD9912_LONGINSN_SET(x: int32) -> int32:
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return (x & 0x1) << 3
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@portable
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def AD9912_LONGINSN_GET(x: TInt32) -> TInt32:
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def AD9912_LONGINSN_GET(x: int32) -> int32:
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return (x >> 3) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_LONGINSN_M_SET(x: TInt32) -> TInt32:
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def AD9912_LONGINSN_M_SET(x: int32) -> int32:
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return (x & 0x1) << 4
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@portable
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def AD9912_LONGINSN_M_GET(x: TInt32) -> TInt32:
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def AD9912_LONGINSN_M_GET(x: int32) -> int32:
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return (x >> 4) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SOFTRESET_M_SET(x: TInt32) -> TInt32:
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def AD9912_SOFTRESET_M_SET(x: int32) -> int32:
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return (x & 0x1) << 5
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@portable
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def AD9912_SOFTRESET_M_GET(x: TInt32) -> TInt32:
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def AD9912_SOFTRESET_M_GET(x: int32) -> int32:
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return (x >> 5) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_LSBFIRST_M_SET(x: TInt32) -> TInt32:
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def AD9912_LSBFIRST_M_SET(x: int32) -> int32:
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return (x & 0x1) << 6
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@portable
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def AD9912_LSBFIRST_M_GET(x: TInt32) -> TInt32:
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def AD9912_LSBFIRST_M_GET(x: int32) -> int32:
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return (x >> 6) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SDOACTIVE_M_SET(x: TInt32) -> TInt32:
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def AD9912_SDOACTIVE_M_SET(x: int32) -> int32:
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return (x & 0x1) << 7
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@portable
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def AD9912_SDOACTIVE_M_GET(x: TInt32) -> TInt32:
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def AD9912_SDOACTIVE_M_GET(x: int32) -> int32:
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return (x >> 7) & 0x1
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@ -83,118 +83,118 @@ AD9912_PRODIDH = 0x003
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AD9912_SER_OPT1 = 0x004
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# default: 0x00, access: R/W
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@portable
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def AD9912_READ_BUF_SET(x: TInt32) -> TInt32:
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def AD9912_READ_BUF_SET(x: int32) -> int32:
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return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_READ_BUF_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_READ_BUF_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
|
||||
AD9912_SER_OPT2 = 0x005
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_RED_UPDATE_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_RED_UPDATE_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_RED_UPDATE_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_RED_UPDATE_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
|
||||
AD9912_PWRCNTRL1 = 0x010
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PD_DIGITAL_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_DIGITAL_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_PD_DIGITAL_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_DIGITAL_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PD_FULL_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_FULL_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 1
|
||||
|
||||
@portable
|
||||
def AD9912_PD_FULL_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_FULL_GET(x: int32) -> int32:
|
||||
return (x >> 1) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PD_SYSCLK_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_SYSCLK_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 4
|
||||
|
||||
@portable
|
||||
def AD9912_PD_SYSCLK_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_SYSCLK_GET(x: int32) -> int32:
|
||||
return (x >> 4) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_EN_DOUBLER_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_EN_DOUBLER_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 5
|
||||
|
||||
@portable
|
||||
def AD9912_EN_DOUBLER_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_EN_DOUBLER_GET(x: int32) -> int32:
|
||||
return (x >> 5) & 0x1
|
||||
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_EN_CMOS_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_EN_CMOS_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 6
|
||||
|
||||
@portable
|
||||
def AD9912_EN_CMOS_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_EN_CMOS_GET(x: int32) -> int32:
|
||||
return (x >> 6) & 0x1
|
||||
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_PD_HSTL_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_HSTL_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_PD_HSTL_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_HSTL_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
AD9912_PWRCNTRL2 = 0x012
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_DDS_RESET_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_DDS_RESET_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_DDS_RESET_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_DDS_RESET_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
|
||||
AD9912_PWRCNTRL3 = 0x013
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_S_DIV_RESET_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV_RESET_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 1
|
||||
|
||||
@portable
|
||||
def AD9912_S_DIV_RESET_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV_RESET_GET(x: int32) -> int32:
|
||||
return (x >> 1) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_S_DIV2_RESET_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV2_RESET_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 3
|
||||
|
||||
@portable
|
||||
def AD9912_S_DIV2_RESET_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV2_RESET_GET(x: int32) -> int32:
|
||||
return (x >> 3) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PD_FUND_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_FUND_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_PD_FUND_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PD_FUND_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
|
|
@ -203,38 +203,38 @@ AD9912_N_DIV = 0x020
|
|||
AD9912_PLLCFG = 0x022
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PLL_ICP_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PLL_ICP_SET(x: int32) -> int32:
|
||||
return (x & 0x3) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_PLL_ICP_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PLL_ICP_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x3
|
||||
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_VCO_RANGE_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_VCO_RANGE_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 2
|
||||
|
||||
@portable
|
||||
def AD9912_VCO_RANGE_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_VCO_RANGE_GET(x: int32) -> int32:
|
||||
return (x >> 2) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_PLL_REF2X_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_PLL_REF2X_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 3
|
||||
|
||||
@portable
|
||||
def AD9912_PLL_REF2X_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_PLL_REF2X_GET(x: int32) -> int32:
|
||||
return (x >> 3) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_VCO_AUTO_RANGE_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_VCO_AUTO_RANGE_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_VCO_AUTO_RANGE_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_VCO_AUTO_RANGE_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
|
|
@ -245,20 +245,20 @@ AD9912_S_DIVH = 0x105
|
|||
AD9912_S_DIV_CFG = 0x106
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_S_DIV2_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV2_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_S_DIV2_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV2_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_S_DIV_FALL_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV_FALL_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_S_DIV_FALL_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_S_DIV_FALL_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
|
|
@ -281,31 +281,31 @@ AD9912_POW1 = 0x1ad
|
|||
AD9912_HSTL = 0x200
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_HSTL_CFG_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSTL_CFG_SET(x: int32) -> int32:
|
||||
return (x & 0x3) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_HSTL_CFG_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSTL_CFG_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x3
|
||||
|
||||
# default: 0x01, access: R/W
|
||||
@portable
|
||||
def AD9912_HSTL_OPOL_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSTL_OPOL_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 4
|
||||
|
||||
@portable
|
||||
def AD9912_HSTL_OPOL_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSTL_OPOL_GET(x: int32) -> int32:
|
||||
return (x >> 4) & 0x1
|
||||
|
||||
|
||||
AD9912_CMOS = 0x201
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_CMOS_MUX_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_CMOS_MUX_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_CMOS_MUX_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_CMOS_MUX_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0x1
|
||||
|
||||
|
||||
|
|
@ -316,29 +316,29 @@ AD9912_FSC1 = 0x40c
|
|||
AD9912_HSR_A_CFG = 0x500
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_A_HARMONIC_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_HARMONIC_SET(x: int32) -> int32:
|
||||
return (x & 0xf) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_A_HARMONIC_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_HARMONIC_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0xf
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_A_MAG2X_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_MAG2X_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 6
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_A_MAG2X_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_MAG2X_GET(x: int32) -> int32:
|
||||
return (x >> 6) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_A_EN_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_EN_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_A_EN_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_A_EN_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
|
|
@ -351,29 +351,29 @@ AD9912_HSR_A_POW1 = 0x504
|
|||
AD9912_HSR_B_CFG = 0x505
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_B_HARMONIC_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_HARMONIC_SET(x: int32) -> int32:
|
||||
return (x & 0xf) << 0
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_B_HARMONIC_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_HARMONIC_GET(x: int32) -> int32:
|
||||
return (x >> 0) & 0xf
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_B_MAG2X_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_MAG2X_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 6
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_B_MAG2X_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_MAG2X_GET(x: int32) -> int32:
|
||||
return (x >> 6) & 0x1
|
||||
|
||||
# default: 0x00, access: R/W
|
||||
@portable
|
||||
def AD9912_HSR_B_EN_SET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_EN_SET(x: int32) -> int32:
|
||||
return (x & 0x1) << 7
|
||||
|
||||
@portable
|
||||
def AD9912_HSR_B_EN_GET(x: TInt32) -> TInt32:
|
||||
def AD9912_HSR_B_EN_GET(x: int32) -> int32:
|
||||
return (x >> 7) & 0x1
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue