forked from M-Labs/artiq
wrpll: DDMTD sampler double latching
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@ -6,21 +6,34 @@ from misoc.interconnect.csr import *
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class DDMTDSamplerExtFF(Module):
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class DDMTDSamplerExtFF(Module):
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def __init__(self, ddmtd_inputs):
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def __init__(self, ddmtd_inputs):
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self.rec_clk = Signal()
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self.main_xo = Signal()
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# # #
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# TODO: s/h timing at FPGA pads
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# TODO: s/h timing at FPGA pads
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if hasattr(ddmtd_inputs, "rec_clk"):
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if hasattr(ddmtd_inputs, "rec_clk"):
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self.rec_clk = ddmtd_inputs.rec_clk
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rec_clk_1 = ddmtd_inputs.rec_clk
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else:
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else:
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self.rec_clk = Signal()
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rec_clk_1 = Signal()
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self.specials += Instance("IBUFDS",
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.rec_clk_p, i_IB=ddmtd_inputs.rec_clk_n,
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i_I=ddmtd_inputs.rec_clk_p, i_IB=ddmtd_inputs.rec_clk_n,
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o_O=self.rec_clk)
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o_O=rec_clk_1)
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if hasattr(ddmtd_inputs, "main_xo"):
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if hasattr(ddmtd_inputs, "main_xo"):
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self.main_xo = ddmtd_inputs.main_xo
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main_xo_1 = ddmtd_inputs.main_xo
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else:
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else:
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self.main_xo = Signal()
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main_xo_1 = Signal()
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self.specials += Instance("IBUFDS",
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self.specials += Instance("IBUFDS",
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i_I=ddmtd_inputs.main_xo_p, i_IB=ddmtd_inputs.main_xo_n,
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i_I=ddmtd_inputs.main_xo_p, i_IB=ddmtd_inputs.main_xo_n,
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o_O=self.main_xo)
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o_O=main_xo_1)
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self.specials += [
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=rec_clk_1, o_Q=self.rec_clk,
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attr={("IOB", "TRUE")}),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_xo_1, o_Q=self.main_xo,
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attr={("IOB", "TRUE")}),
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]
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class DDMTDSamplerGTP(Module):
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class DDMTDSamplerGTP(Module):
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@ -28,20 +41,30 @@ class DDMTDSamplerGTP(Module):
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self.rec_clk = Signal()
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self.rec_clk = Signal()
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self.main_xo = Signal()
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self.main_xo = Signal()
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# # #
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# Getting the main XO signal from IBUFDS_GTE2 is problematic because
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# Getting the main XO signal from IBUFDS_GTE2 is problematic because
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# the transceiver PLL craps out if an improper clock signal is applied,
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# the transceiver PLL craps out if an improper clock signal is applied,
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# so we are disabling the buffer until the clock is stable.
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# so we are disabling the buffer until the clock is stable.
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main_xo_se = Signal()
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main_xo_se = Signal()
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rec_clk_1 = Signal()
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main_xo_1 = Signal()
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self.specials += [
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self.specials += [
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Instance("IBUFDS",
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Instance("IBUFDS",
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i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
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i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
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o_O=main_xo_se),
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o_O=main_xo_se),
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Instance("FD", i_C=ClockSignal("helper"),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=gtp.cd_rtio_rx0.clk, o_Q=self.rec_clk,
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i_D=gtp.cd_rtio_rx0.clk, o_Q=rec_clk_1,
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attr={("DONT_TOUCH", "TRUE")}),
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attr={("DONT_TOUCH", "TRUE")}),
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Instance("FD", i_C=ClockSignal("helper"),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_xo_se, o_Q=self.main_xo,
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i_D=rec_clk_1, o_Q=self.rec_clk,
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attr={("DONT_TOUCH", "TRUE")}),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_xo_se, o_Q=main_xo_1,
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attr={("IOB", "TRUE")}),
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attr={("IOB", "TRUE")}),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_xo_1, o_Q=self.main_xo,
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attr={("DONT_TOUCH", "TRUE")}),
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]
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]
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