From de7d64d482dcd51755be93040562896528670b68 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 21 Jun 2018 22:32:41 +0800 Subject: [PATCH] sayma: clock JESD204 from GTP CLK2 This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO. --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 2 +- artiq/firmware/runtime/main.rs | 4 ++-- artiq/gateware/jesd204_tools.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 3ecea703f..a2c4a644f 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -171,7 +171,7 @@ pub mod hmc7043 { (true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF (false, 0, 0x08), // 4: ADC2_CLK (false, 0, 0x08), // 5: ADC2_SYSREF - (false, 0, 0x08), // 6: GTP_CLK2 + (true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2 (true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS (true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1 (false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK diff --git a/artiq/firmware/runtime/main.rs b/artiq/firmware/runtime/main.rs index 1e39f9968..cfd420e04 100644 --- a/artiq/firmware/runtime/main.rs +++ b/artiq/firmware/runtime/main.rs @@ -57,9 +57,9 @@ mod moninj; mod analyzer; #[cfg(has_ad9154)] -const SYSREF_PHASE_FPGA: u16 = 32; +const SYSREF_PHASE_FPGA: u16 = 20; #[cfg(has_ad9154)] -const SYSREF_PHASE_DAC: u16 = 61; +const SYSREF_PHASE_DAC: u16 = 31; fn startup() { irq::set_mask(0); diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 33d0ca025..3471073ea 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -26,7 +26,7 @@ class UltrascaleCRG(Module, AutoCSR): self.clock_domains.cd_jesd = ClockDomain() refclk2 = Signal() - refclk_pads = platform.request("dac_refclk", 0) + refclk_pads = platform.request("dac_refclk", 1) platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq) self.specials += [ Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00,