From de4712373712a139e952f8c6610df18a17a23aee Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 5 Nov 2016 00:24:00 +0800
Subject: [PATCH] drtio: connect RST and LOCKED on 7series RXSynchronizer MMCM

---
 artiq/gateware/drtio/transceiver/gtx_7series.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index 0780982ca..61e9287a7 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -223,6 +223,7 @@ class RXSynchronizer(Module, AutoCSR):
             Instance("MMCME2_ADV",
                 p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
                 i_CLKIN1=ClockSignal("rtio_rx"),
+                i_RST=ResetSignal("rtio_rx"),
                 i_CLKINSEL=1,  # yes, 1=CLKIN1 0=CLKIN2
 
                 p_CLKFBOUT_MULT_F=mmcm_mult,
@@ -237,6 +238,7 @@ class RXSynchronizer(Module, AutoCSR):
 
                 p_CLKOUT0_USE_FINE_PS="TRUE",
                 o_CLKOUT0=mmcm_output,
+                o_LOCKED=mmcm_locked,
 
                 i_PSCLK=ClockSignal(),
                 i_PSEN=self.phase_shift.re,