forked from M-Labs/artiq
kc705_drtio_satellite: set output dir
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@ -160,10 +160,13 @@ def main():
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parser = argparse.ArgumentParser(description="KC705 DRTIO satellite")
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parser = argparse.ArgumentParser(description="KC705 DRTIO satellite")
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parser.add_argument("--toolchain", default="vivado",
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parser.add_argument("--toolchain", default="vivado",
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help="FPGA toolchain to use: ise, vivado")
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help="FPGA toolchain to use: ise, vivado")
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parser.add_argument("--output-dir", default="drtiosat_kc705",
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help="output directory for generated "
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"source files and binaries")
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args = parser.parse_args()
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args = parser.parse_args()
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top = Satellite(args.toolchain)
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top = Satellite(args.toolchain)
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top.build()
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top.build(build_dir=args.output_dir)
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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main()
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