From ddcc68cff9f52224150f00e42e46fdb107d24e49 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 2 Mar 2018 18:10:57 +0800 Subject: [PATCH] sayma_amc: move bitstream options to migen close #930 --- artiq/gateware/targets/sayma_amc.py | 5 ----- conda/artiq-dev/meta.yaml | 2 +- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index c19b4a653..22038b355 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -146,11 +146,6 @@ class Standalone(MiniSoC, AMPSoC): **kwargs) AMPSoC.__init__(self) platform = self.platform - platform.toolchain.bitstream_commands.extend([ - "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", - "set_property CFGBVS VCCO [current_design]", - "set_property CONFIG_VOLTAGE 3.3 [current_design]", - ]) # forward RTM UART to second FTDI UART channel serial_1 = platform.request("serial", 1) diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml index 7d50b6684..c3a5342be 100644 --- a/conda/artiq-dev/meta.yaml +++ b/conda/artiq-dev/meta.yaml @@ -14,7 +14,7 @@ requirements: run: - python >=3.5.3,<3.6 - setuptools 33.1.1 - - migen 0.7 py35_10+git0996e0b + - migen 0.7 py35_14+git8fcd67a - misoc 0.9 py35_20+git5fed1095 - jesd204b 0.5 - microscope