From db82b11f2986e8d662be512eae0176b6e5103fb3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Nov 2017 10:33:39 +0100 Subject: [PATCH] gateware/serwb/core: cleanup and increase fifo depth --- artiq/gateware/serwb/core.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/serwb/core.py b/artiq/gateware/serwb/core.py index 4435c3e40..61c76a884 100644 --- a/artiq/gateware/serwb/core.py +++ b/artiq/gateware/serwb/core.py @@ -12,10 +12,10 @@ class SERWBCore(Module): depacketizer = Depacketizer(clk_freq) packetizer = Packetizer() self.submodules += depacketizer, packetizer - tx_cdc = stream.AsyncFIFO([("data", 32)], 8) + tx_cdc = stream.AsyncFIFO([("data", 32)], 32) tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serwb_serdes"})(tx_cdc) self.submodules += tx_cdc - rx_cdc = stream.AsyncFIFO([("data", 32)], 8) + rx_cdc = stream.AsyncFIFO([("data", 32)], 32) rx_cdc = ClockDomainsRenamer({"write": "serwb_serdes", "read": "sys"})(rx_cdc) self.submodules += rx_cdc self.comb += [ @@ -25,10 +25,12 @@ class SERWBCore(Module): # core --> serdes packetizer.source.connect(tx_cdc.sink), - If(tx_cdc.source.stb & phy.init.ready, - phy.serdes.tx_data.eq(tx_cdc.source.data) + If(phy.init.ready, + If(tx_cdc.source.stb, + phy.serdes.tx_data.eq(tx_cdc.source.data) + ), + tx_cdc.source.ack.eq(1) ), - tx_cdc.source.ack.eq(phy.init.ready), # serdes --> core rx_cdc.sink.stb.eq(phy.init.ready),