From dac3a78b75447bc8054ecda9af5892cce33b6b0d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 21 Aug 2017 12:35:59 -0400 Subject: [PATCH] serwb: style, use migen, fix imports --- artiq/gateware/serwb/etherbone.py | 2 +- artiq/gateware/serwb/kusphy.py | 2 +- artiq/gateware/serwb/s7phy.py | 2 +- artiq/gateware/test/serwb/test_etherbone.py | 22 ++++++++++----------- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/artiq/gateware/serwb/etherbone.py b/artiq/gateware/serwb/etherbone.py index 8337b4389..8add43044 100644 --- a/artiq/gateware/serwb/etherbone.py +++ b/artiq/gateware/serwb/etherbone.py @@ -15,7 +15,7 @@ from migen import * from misoc.interconnect import stream from misoc.interconnect import wishbone -from amc_rtm_link.packet import * +from artiq.gateware.serwb.packet import * class Packetizer(Module): diff --git a/artiq/gateware/serwb/kusphy.py b/artiq/gateware/serwb/kusphy.py index ed3716491..4733fb58c 100644 --- a/artiq/gateware/serwb/kusphy.py +++ b/artiq/gateware/serwb/kusphy.py @@ -5,7 +5,7 @@ from migen.genlib.misc import BitSlip from misoc.cores.code_8b10b import Encoder, Decoder -from amc_rtm_link.phy import PhaseDetector +from artiq.gateware.serwb.phy import PhaseDetector class KUSSerdesPLL(Module): diff --git a/artiq/gateware/serwb/s7phy.py b/artiq/gateware/serwb/s7phy.py index 861c38d05..ed1366805 100644 --- a/artiq/gateware/serwb/s7phy.py +++ b/artiq/gateware/serwb/s7phy.py @@ -5,7 +5,7 @@ from migen.genlib.misc import BitSlip from misoc.cores.code_8b10b import Encoder, Decoder -from amc_rtm_link.phy import PhaseDetector +from artiq.gateware.serwb.phy import PhaseDetector class S7SerdesPLL(Module): diff --git a/artiq/gateware/test/serwb/test_etherbone.py b/artiq/gateware/test/serwb/test_etherbone.py index df74b3ccf..248e3f68e 100644 --- a/artiq/gateware/test/serwb/test_etherbone.py +++ b/artiq/gateware/test/serwb/test_etherbone.py @@ -1,15 +1,10 @@ -#!/usr/bin/env python3 +from migen import * -from litex.gen import * +from misoc.interconnect.wishbone import SRAM +from misoc.interconnect.stream import Converter -import sys -sys.path.append("../../gateware/") - -from amc_rtm_link import packet -from amc_rtm_link import etherbone - -from litex.soc.interconnect.wishbone import SRAM -from litex.soc.interconnect.stream import Converter +from artiq.gateware.serwb import packet +from artiq.gateware.serwb import etherbone class DUT(Module): @@ -57,6 +52,7 @@ class DUT(Module): # expose wishbone slave self.wishbone = slave_etherbone.wishbone.bus + def main_generator(dut): for i in range(8): yield from dut.wishbone.write(0x100 + i, i) @@ -64,5 +60,7 @@ def main_generator(dut): data = (yield from dut.wishbone.read(0x100 + i)) print("0x{:08x}".format(data)) -dut = DUT() -run_simulation(dut, main_generator(dut), vcd_name="sim.vcd") + +if __name__ == "__main__": + dut = DUT() + run_simulation(dut, main_generator(dut), vcd_name="sim.vcd")