From d9955fee769a739ab39c4c29e62e4d3825afbfe6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 22 Jun 2018 11:00:56 +0800 Subject: [PATCH] jesd204: make sure IOB FF is used to sample SYSREF at FPGA --- artiq/gateware/jesd204_tools.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 3471073ea..e467a87c9 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -42,6 +42,7 @@ class UltrascaleCRG(Module, AutoCSR): jref = platform.request("dac_sysref") jref_se = Signal() + jref_r = Signal() self.specials += [ Instance("IBUFDS_IBUFDISABLE", p_USE_IBUFDISABLE="TRUE", p_SIM_DEVICE="ULTRASCALE", @@ -51,7 +52,9 @@ class UltrascaleCRG(Module, AutoCSR): # SYSREF normally meets s/h at the FPGA, except during margin # scan and before full initialization. # Be paranoid and use a double-register anyway. - MultiReg(jref_se, self.jref, "jesd") + Instance("FD", i_C=ClockSignal("jesd"), i_D=jref_se, o_Q=jref_r, + attr={("IOB", "TRUE")}), + Instance("FD", i_C=ClockSignal("jesd"), i_D=jref_r, o_Q=self.jref) ]