forked from M-Labs/artiq
sawg: extend phase mode docs
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@ -39,8 +39,11 @@ class Config:
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"""Set the spline evolution divider and current counter value.
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The divider and the spline evolution are synchronized across all
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spline channels within a SAWG channel. The phase accumulator always
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evolves at full speed.
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spline channels within a SAWG channel. The DDS/DUC phase accumulators
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always evolves at full speed.
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.. note:: The spline evolution divider has not been tested extensively
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and is currently considered a technological preview only.
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:param div: Spline evolution divider, such that
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``t_sawg_spline/t_rtio_coarse = div + 1``. Default: ``0``.
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@ -50,16 +53,32 @@ class Config:
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@kernel
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def set_clr(self, clr0: TInt32, clr1: TInt32, clr2: TInt32):
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"""Set the phase clear mode for the three phase accumulators.
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"""Set the accumulator clear mode for the three phase accumulators.
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When the ``clr`` bit for a given phase accumulator is
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set, that phase accumulator will be cleared with every phase RTIO
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command and the output phase will be exactly the phase RTIO value
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("absolute phase update mode").
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When the ``clr`` bit for a given DDS/DUC phase accumulator is
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set, that phase accumulator will be cleared with every phase offset
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RTIO command and the output phase of the DDS/DUC will be
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exactly the phase RTIO value ("absolute phase update mode").
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In turn, when the bit is cleared, the phase RTIO channels only
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provide a phase offset to the current value of the phase
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accumulator ("relative phase update mode").
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.. math::
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q^\prime(t) = p^\prime + (t - t^\prime) f^\prime
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In turn, when the bit is cleared, the phase RTIO channels
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determine a phase offset to the current (carrier-) value of the
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DDS/DUC phase accumulator. This "relative phase update mode" is
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sometimes also called “continuous phase mode”.
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.. math::
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q^\prime(t) = q(t^\prime) + (p^\prime - p) +
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(t - t^\prime) f^\prime
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Where:
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* :math:`q`, :math:`q^\prime`: old/new phase accumulator
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* :math:`p`, :math:`p^\prime`: old/new phase offset
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* :math:`f^\prime`: new frequency
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* :math:`t^\prime`: timestamp of setting new :math:`p`, :math:`f`
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* :math:`t`: running time
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:param clr0: Auto-clear phase accumulator of the ``phase0``/
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``frequency0`` DUC. Default: ``True``
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@ -83,7 +102,8 @@ class Config:
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description of ``i_enable`` and ``q_enable``.
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.. note:: Quadrature data from the buddy channel is currently
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ignored in the SAWG gateware and not added to the DAC output.
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a technological preview only. The data is ignored in the SAWG
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gateware and not added to the DAC output.
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This is equivalent to the ``q_enable`` switch always being ``0``.
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:param i_enable: Controls adding the in-phase
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