forked from M-Labs/artiq
kc705: add TTLs and shift register driver for FMC DIO
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4deeccbead
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@ -34,7 +34,7 @@ device_db = {
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"class": "DDSGroupAD9914",
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"arguments": {
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"sysclk": 3e9,
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"first_dds_bus_channel": 29,
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"first_dds_bus_channel": 32,
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"dds_bus_count": 2,
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"dds_channel_count": 3
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}
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@ -131,6 +131,34 @@ device_db = {
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"arguments": {"channel": 26}
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},
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# FMC DIO used to connect to Zotino
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"fmcdio_dirctl_clk": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 27}
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},
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"fmcdio_dirctl_ser": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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},
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"fmcdio_dirctl_latch": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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"fmcdio_dirctl": {
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"type": "local",
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"module": "artiq.coredevice.shiftreg",
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"class": "ShiftReg",
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"arguments": {"clk": "fmcdio_dirctl_clk",
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"ser": "fmcdio_dirctl_ser",
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"latch": "fmcdio_dirctl_latch"}
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},
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# DAC
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"spi_ams101": {
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"type": "local",
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@ -148,13 +176,13 @@ device_db = {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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"arguments": {"channel": 27}
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"arguments": {"channel": 30}
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},
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"ttl_zotino_ldac": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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"arguments": {"channel": 31}
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},
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"dac_zotino": {
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"type": "local",
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@ -168,20 +196,20 @@ device_db = {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 29, "channel": 0},
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"arguments": {"bus_channel": 32, "channel": 0},
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"comment": "Comments work in DDS panel as well"
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},
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"dds1": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 29, "channel": 1}
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"arguments": {"bus_channel": 32, "channel": 1}
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},
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"dds2": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 29, "channel": 2}
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"arguments": {"bus_channel": 32, "channel": 2}
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},
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# Controllers
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@ -98,35 +98,41 @@ _ams101_dac = [
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]
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_sdcard_spi_33 = [
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("sdcard_spi_33", 0,
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20"), Misc("PULLUP")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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)
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]
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_zotino = [
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("fmcdio_dirctl", 0,
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Subsignal("clk", Pins("HPC:LA32_N")),
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Subsignal("ser", Pins("HPC:LA33_P")),
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Subsignal("latch", Pins("HPC:LA32_P")),
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IOStandard("LVCMOS33")
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),
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("zotino_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA08_P")),
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Subsignal("mosi", Pins("HPC:LA09_P")),
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Subsignal("miso", Pins("HPC:LA10_P")),
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Subsignal("cs_n", Pins("HPC:LA11_P")),
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IOStandard("LVDS_25")
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),
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),
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("zotino_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA08_N")),
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Subsignal("mosi", Pins("HPC:LA09_N")),
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Subsignal("miso", Pins("HPC:LA10_N")),
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Subsignal("cs_n", Pins("HPC:LA11_N")),
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IOStandard("LVDS_25")
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),
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),
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("zotino_ldac", 0,
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Subsignal("p", Pins("HPC:LA13_P")),
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Subsignal("n", Pins("HPC:LA13_N")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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)
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)
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]
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class _NIST_Ions(MiniSoC, AMPSoC):
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@ -254,13 +260,19 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0))
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phy = spi.SPIMaster(platform.request("sdcard_spi_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0),
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self.platform.request("zotino_spi_n", 0))
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fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
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for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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phy = ttl_simple.Output(s)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p"),
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self.platform.request("zotino_spi_n"))
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self.submodules += sdac_phy
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rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
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@ -68,7 +68,13 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| 21 | LA32_P | Clock |
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+--------------------+-----------------------+--------------+
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| 28 | ZOTINO_LDAC | Output |
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| 27 | FMCDIO_DIRCTL_CLK | Output |
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+--------------------+-----------------------+--------------+
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| 28 | FMCDIO_DIRCTL_SER | Output |
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+--------------------+-----------------------+--------------+
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| 29 | FMCDIO_DIRCTL_LATCH | Output |
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+--------------------+-----------------------+--------------+
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| 31 | ZOTINO_LDAC | Output |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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@ -86,11 +92,14 @@ The board has RTIO SPI buses mapped as follows:
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+--------------+--------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+--------------+--------------+--------------+------------+
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| 27 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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+--------------+--------------+--------------+--------------+------------+
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The DDS bus is on channel 29.
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The DDS bus is on channel 32.
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This configuration supports a Zotino connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0.
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The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`.
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NIST QC2
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++++++++
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